Chapter 6 Multi Core Architecture - Revision history

Drdivech at 03:52, 25 February 2010

2010-02-25T03:52:26Z

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	The placement policy is the first step in managing a cache. This decides where a block in memory can be placed in the cache. The placement policies are:		The placement policy is the first step in managing a cache. This decides where a block in memory can be placed in the cache. The placement policies are:

	1. === '''Direct mapped''' ===		=== '''Direct mapped''' ===
	If each block has only one place where it can appear in a cache, it is called direct- mapping. It is also known as one way set associative.<sup>[6]</sup> <br />		If each block has only one place where it can appear in a cache, it is called direct- mapping. It is also known as one way set associative.<sup>[6]</sup> <br />
	The main memory address (32 bits) is broken down as: (Assumed 8 blocks and 8 lines in cache.)		The main memory address (32 bits) is broken down as: (Assumed 8 blocks and 8 lines in cache.)
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	Each line has its own tag associated with it. The index tells which row of cache to look at. To search for a word in the cache, compare the tag bits of the address with the tag of the line. If it matches, the block is in the cache. It is a cache hit. Then select the corresponding word from that line.		Each line has its own tag associated with it. The index tells which row of cache to look at. To search for a word in the cache, compare the tag bits of the address with the tag of the line. If it matches, the block is in the cache. It is a cache hit. Then select the corresponding word from that line.

	2.=== '''Fully Associative''' ===		=== '''Fully Associative''' ===
	If any line can store the contents of any memory location, it is known as fully associative cache. Hence, no index bits are required. <br />		If any line can store the contents of any memory location, it is known as fully associative cache. Hence, no index bits are required. <br />
	The main memory address (32 bits) is broken down as:		The main memory address (32 bits) is broken down as:
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	It is also known as Content Addressable Memory. To search for a word in the cache, compare the tag bits of the address with the tag of all lines in the cache simultaneously. If any one matches, the word is in the cache. Then select the corresponding word from that line.		It is also known as Content Addressable Memory. To search for a word in the cache, compare the tag bits of the address with the tag of all lines in the cache simultaneously. If any one matches, the word is in the cache. Then select the corresponding word from that line.

	3.=== '''Set Associative''' ===		=== '''Set Associative''' ===

	[[Image:table4.jpg]]		[[Image:table4.jpg]]

Drdivech at 03:51, 25 February 2010

2010-02-25T03:51:54Z

← Older revision		Revision as of 03:51, 25 February 2010
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	The placement policy is the first step in managing a cache. This decides where a block in memory can be placed in the cache. The placement policies are:		The placement policy is the first step in managing a cache. This decides where a block in memory can be placed in the cache. The placement policies are:

	1. ==='''Direct mapped'''===		1. === '''Direct mapped''' ===
	If each block has only one place where it can appear in a cache, it is called direct- mapping. It is also known as one way set associative.<sup>[6]</sup> <br />		If each block has only one place where it can appear in a cache, it is called direct- mapping. It is also known as one way set associative.<sup>[6]</sup> <br />
	The main memory address (32 bits) is broken down as: (Assumed 8 blocks and 8 lines in cache.)		The main memory address (32 bits) is broken down as: (Assumed 8 blocks and 8 lines in cache.)
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	Each line has its own tag associated with it. The index tells which row of cache to look at. To search for a word in the cache, compare the tag bits of the address with the tag of the line. If it matches, the block is in the cache. It is a cache hit. Then select the corresponding word from that line.		Each line has its own tag associated with it. The index tells which row of cache to look at. To search for a word in the cache, compare the tag bits of the address with the tag of the line. If it matches, the block is in the cache. It is a cache hit. Then select the corresponding word from that line.

	2.=== '''Fully Associative'''===		2.=== '''Fully Associative''' ===
	If any line can store the contents of any memory location, it is known as fully associative cache. Hence, no index bits are required. <br />		If any line can store the contents of any memory location, it is known as fully associative cache. Hence, no index bits are required. <br />
	The main memory address (32 bits) is broken down as:		The main memory address (32 bits) is broken down as:
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	It is also known as Content Addressable Memory. To search for a word in the cache, compare the tag bits of the address with the tag of all lines in the cache simultaneously. If any one matches, the word is in the cache. Then select the corresponding word from that line.		It is also known as Content Addressable Memory. To search for a word in the cache, compare the tag bits of the address with the tag of all lines in the cache simultaneously. If any one matches, the word is in the cache. Then select the corresponding word from that line.

	3.==='''Set Associative'''===		3.=== '''Set Associative''' ===

	[[Image:table4.jpg]]		[[Image:table4.jpg]]
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	L1- I: 32 KB/ core, L1- D: 32 KB/ core, L2: 256 KB/ core, L3: 26 MB/ chip.		L1- I: 32 KB/ core, L1- D: 32 KB/ core, L2: 256 KB/ core, L3: 26 MB/ chip.

	== '''~~Write Policies'''~~ used in recent multi core architectures''' ==		== '''WRITE POLICIES used in recent multi core architectures''' ==

	1. '''Intel Pentium Processors''': <sup>[10]</sup> Mainly 2 bits control the cache. CD (cache disable) and NW (not write through)		1. '''Intel Pentium Processors''': <sup>[10]</sup> Mainly 2 bits control the cache. CD (cache disable) and NW (not write through)
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	An UC <sup>[11]</sup> ('''Uncacheable''') line is not put into the cache. A UC hit to the L1 or L2 cache invalidates the entry.		An UC <sup>[11]</sup> ('''Uncacheable''') line is not put into the cache. A UC hit to the L1 or L2 cache invalidates the entry.
	Cache consistency: MESI (Modified, Exclusive, Shared, Invalid) policy is used.		Cache consistency: MESI (Modified, Exclusive, Shared, Invalid) policy is used.


	2.'''Intel IA 32 IA64 architecture''': <sup>[12]</sup> In IA 32, the number of processor sharing the cache is one plus value represented by CPUID.4.EAX [25:14]		2.'''Intel IA 32 IA64 architecture''': <sup>[12]</sup> In IA 32, the number of processor sharing the cache is one plus value represented by CPUID.4.EAX [25:14]

Drdivech at 03:50, 25 February 2010

2010-02-25T03:50:10Z

Drdivech at 03:47, 25 February 2010

2010-02-25T03:47:22Z

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	A '''victim cache''' is a cache used to hold blocks evicted from a CPU cache upon replacement. When main cache evicts a block, the victim cache will take the evicted block. This block is called the victim block. When the main cache misses, it searches the victim cache for recently evicted blocks. So, a hit in victim cache means the main cache doesn’t have to go to the next level of memory.		A '''victim cache''' is a cache used to hold blocks evicted from a CPU cache upon replacement. When main cache evicts a block, the victim cache will take the evicted block. This block is called the victim block. When the main cache misses, it searches the victim cache for recently evicted blocks. So, a hit in victim cache means the main cache doesn’t have to go to the next level of memory.

	=== '''~~TLB~~''' ===		=== '''Translation LookAside Buffer''' ===
	The '''TLB''' is a small cache holding recently used virtual-to-physical address translations. TLB is a hardware cache that sits alongside the L1 instruction and data caches.		The '''TLB''' is a small cache holding recently used virtual-to-physical address translations. TLB is a hardware cache that sits alongside the L1 instruction and data caches.

Drdivech at 03:46, 25 February 2010

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	=== '''Victim Cache''' ===		=== '''Victim Cache''' ===
	A victim cache is a cache used to hold blocks evicted from a CPU cache upon replacement. When main cache evicts a block, the victim cache will take the evicted block. This block is called the victim block. When the main cache misses, it searches the victim cache for recently evicted blocks. So, a hit in victim cache means the main cache doesn’t have to go to the next level of memory.		A '''victim cache''' is a cache used to hold blocks evicted from a CPU cache upon replacement. When main cache evicts a block, the victim cache will take the evicted block. This block is called the victim block. When the main cache misses, it searches the victim cache for recently evicted blocks. So, a hit in victim cache means the main cache doesn’t have to go to the next level of memory.

	=== '''TLB''' ===		=== '''TLB''' ===
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	Intel Advanced '''Smart Cache'''<sup>[5]</sup> is a multi-core optimized cache that improves performance by increasing the probability that each execution core of a dual-core processor can access data from a higher-performance, more-efficient cache subsystem. To accomplish this, Intel Core micro architecture shares the Level 2 (L2) cache between the cores. If one of the cores is inactive, the other core will have access to the full cache. It provides a peak transfer rate of 96 GB/sec (at 3 GHz frequency).		Intel Advanced '''Smart Cache'''<sup>[5]</sup> is a multi-core optimized cache that improves performance by increasing the probability that each execution core of a dual-core processor can access data from a higher-performance, more-efficient cache subsystem. To accomplish this, Intel Core micro architecture shares the Level 2 (L2) cache between the cores. If one of the cores is inactive, the other core will have access to the full cache. It provides a peak transfer rate of 96 GB/sec (at 3 GHz frequency).

	==='''Parameters of a cache:'''=== ~~<br />~~		=== '''Parameters of a cache:''' ===
	1. Size: cache data storage. <br />		1. Size: cache data storage. <br />
	2. Associativity: Number of blocks in a set <br />		2. Associativity: Number of blocks in a set <br />

Drdivech at 03:45, 25 February 2010

2010-02-25T03:45:40Z

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	The term '''multicore''' means two or more independent cores. The term '''architecture''' means the design/layout of a particular idea. Hence the combined term multicore architecture simply means the integration of cores and its layout. For e.g. '''dual core''' means each processor contains 2 independent cores.		The term '''multicore''' means two or more independent cores. The term '''architecture''' means the design/layout of a particular idea. Hence the combined term multicore architecture simply means the integration of cores and its layout. For e.g. '''dual core''' means each processor contains 2 independent cores.

	=='''NUMA ~~architectures~~'''==		=='''NUMA architecture'''==
	The term '''NUMA''' is an acronym for Non Uniform Memory Access. It is one way of organizing the '''MIMD''' (Multiple Instruction Multiple Data: independent processors are connected together to form a multiprocessor system.) architecture. NUMA is also known as distributed shared memory. Each processor has an independent cache, memory and they are connected to a common interconnection network like a crossbar, mesh, hypercube, etc.		The term '''NUMA''' is an acronym for Non Uniform Memory Access. It is one way of organizing the '''MIMD''' (Multiple Instruction Multiple Data: independent processors are connected together to form a multiprocessor system.) architecture. NUMA is also known as distributed shared memory. Each processor has an independent cache, memory and they are connected to a common interconnection network like a crossbar, mesh, hypercube, etc.

Drdivech at 03:45, 25 February 2010

2010-02-25T03:45:15Z

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	[[Image:table31.jpg]] [[Image:table32.jpg]]		[[Image:table31.jpg]] [[Image:table32.jpg]]

	== ~~Recent~~ '''NUMA''' ~~architectures~~==		== RECENT '''NUMA''' ARCHITECTURES==

	1. 4 '''Opteron 875''' dual core processors: 1 L1- D cache per core (2 per socket), size: 65 KB		1. 4 '''Opteron 875''' dual core processors: 1 L1- D cache per core (2 per socket), size: 65 KB

Drdivech at 03:44, 25 February 2010

2010-02-25T03:44:38Z

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	== '''REFERENCES''' == ~~<br />~~		=='''REFERENCES'''==

	[1]: http://www.karbosguide.com/books/pcarchitecture/chapter10.htm <br />		[1]: http://www.karbosguide.com/books/pcarchitecture/chapter10.htm <br />

Drdivech at 03:43, 25 February 2010

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	== '''REFERENCES'''== <br />		== '''REFERENCES''' == <br />

	[1]: http://www.karbosguide.com/books/pcarchitecture/chapter10.htm <br />		[1]: http://www.karbosguide.com/books/pcarchitecture/chapter10.htm <br />

Drdivech at 03:43, 25 February 2010

2010-02-25T03:43:36Z

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	=='''WRITE POLICY'''==		=='''WRITE POLICY'''==

	1. === '''Write Through''' ===		=== '''Write Through''' ===
	Whenever a value is written in the cache, it is immediately written in the next level of memory hierarchy. The main advantage is that both levels have the recent updated value at all times. No dirty bit is required. The disadvantage is that since it writes every time, it consumes a lot of bandwidth. A bit stored in the cache can flip its value when struck by alpha particles resulting in soft errors<sup>[4]</sup>. The effect of this is that the value in the cache is lost. Since, the lower level of cache contains the same updated value, it is safe to discard the block, as it can be easily re fetched. So, only error detection is enough.		Whenever a value is written in the cache, it is immediately written in the next level of memory hierarchy. The main advantage is that both levels have the recent updated value at all times. No dirty bit is required. The disadvantage is that since it writes every time, it consumes a lot of bandwidth. A bit stored in the cache can flip its value when struck by alpha particles resulting in soft errors<sup>[4]</sup>. The effect of this is that the value in the cache is lost. Since, the lower level of cache contains the same updated value, it is safe to discard the block, as it can be easily re fetched. So, only error detection is enough.

	2.=== '''Write Back''' ===		=== '''Write Back''' ===
	The next level of memory hierarchy is not updated as soon as a value is written in the cache, but is updated only when a block is evicted from the cache. To cope up with the issue of having the most recent value, a dirty bit is associated with the cache block. When there is a write to the cache, the dirty bit is set 1. So, if this block were to be evicted, indication of dirty bit being 1, will make the block to be written back to the main memory. When a new block is written in cache, the dirty bit is made 0. Since, lower level of cache does not contain the same updated value, error correction is necessary.		The next level of memory hierarchy is not updated as soon as a value is written in the cache, but is updated only when a block is evicted from the cache. To cope up with the issue of having the most recent value, a dirty bit is associated with the cache block. When there is a write to the cache, the dirty bit is set 1. So, if this block were to be evicted, indication of dirty bit being 1, will make the block to be written back to the main memory. When a new block is written in cache, the dirty bit is made 0. Since, lower level of cache does not contain the same updated value, error correction is necessary.

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	[[Image:table31.jpg]] [[Image:table32.jpg]]		[[Image:table31.jpg]] [[Image:table32.jpg]]

	== ~~RECENT~~ '''NUMA''' ~~ARCHITECTURES~~==		== '''RECENT NUMA ARCHITECTURES''' ==

	1. 4 '''Opteron 875''' dual core processors: 1 L1- D cache per core (2 per socket), size: 65 KB		1. 4 '''Opteron 875''' dual core processors: 1 L1- D cache per core (2 per socket), size: 65 KB
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	L1- I: 32 KB/ core, L1- D: 32 KB/ core, L2: 256 KB/ core, L3: 26 MB/ chip.		L1- I: 32 KB/ core, L1- D: 32 KB/ core, L2: 256 KB/ core, L3: 26 MB/ chip.

	== '''Write Policies''' used in recent multi core architectures == ~~<br />~~		== '''Write Policies''' used in recent multi core architectures''' ==

	1. '''Intel Pentium Processors''': <sup>[10]</sup> Mainly 2 bits control the cache. CD (cache disable) and NW (not write through)		1. '''Intel Pentium Processors''': <sup>[10]</sup> Mainly 2 bits control the cache. CD (cache disable) and NW (not write through)
	<center>CD= 1: cache disabled, CD=0: enables the cache</center>		<center>CD= 1: cache disabled, CD=0: enables the cache</center>
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	An UC <sup>[11]</sup> ('''Uncacheable''') line is not put into the cache. A UC hit to the L1 or L2 cache invalidates the entry.		An UC <sup>[11]</sup> ('''Uncacheable''') line is not put into the cache. A UC hit to the L1 or L2 cache invalidates the entry.
	Cache consistency: MESI (Modified, Exclusive, Shared, Invalid) policy is used.		Cache consistency: MESI (Modified, Exclusive, Shared, Invalid) policy is used.


	2.'''Intel IA 32 IA64 architecture''': <sup>[12]</sup> In IA 32, the number of processor sharing the cache is one plus value represented by CPUID.4.EAX [25:14]		2.'''Intel IA 32 IA64 architecture''': <sup>[12]</sup> In IA 32, the number of processor sharing the cache is one plus value represented by CPUID.4.EAX [25:14]
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	If the programmer specifies a non-temporal store to UC or WP memory types, then the store behaves like an uncacheable store. There is no conflict if a non temporal store to WC is specified. If the programmer specifies a non-temporal store to WB or WT memory types, and if the data is in the cache, will ensure consistency. However, if it is a miss, the transaction is subject to all WC memory semantics, which will not write allocate.		If the programmer specifies a non-temporal store to UC or WP memory types, then the store behaves like an uncacheable store. There is no conflict if a non temporal store to WC is specified. If the programmer specifies a non-temporal store to WB or WT memory types, and if the data is in the cache, will ensure consistency. However, if it is a miss, the transaction is subject to all WC memory semantics, which will not write allocate.


	'''3'''.Intel's '''Celeron''' and '''Xeon''' based on '''Netburst microarchitecture''' (i.e. based on Pentium 4) will have the same specs as Pentium 4 but with different L2 cache size, while Celeron and Xeon based on '''Core microarchitecture''' (i.e. based on Core 2 Duo) will have the same specs as Core 2 Duo but with different L2 cache size. <br />		'''3'''.Intel's '''Celeron''' and '''Xeon''' based on '''Netburst microarchitecture''' (i.e. based on Pentium 4) will have the same specs as Pentium 4 but with different L2 cache size, while Celeron and Xeon based on '''Core microarchitecture''' (i.e. based on Core 2 Duo) will have the same specs as Core 2 Duo but with different L2 cache size. <br />