CSC 456 Fall 2013/1d vb - Revision history

Bvuong: /* Power Consumption vs. Performance */

2013-09-17T16:24:33Z

Power Consumption vs. Performance

← Older revision		Revision as of 16:24, 17 September 2013
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	Along with performance, power is another concern in microarchitectural design. There have been multiple studies on what optimal pipeline depth when considering both performance and power. Srinivasan stated that majority of power used is related to latches, including clocking and the leakage of power per latch. The number of latches grows super linearly with the number of pipeline stages according to Srinivasan. The overall power/performance is improved with the number of pipeline stages, as illustrated in the graph.		Along with performance, power is another concern in microarchitectural design. There have been multiple studies on what optimal pipeline depth when considering both performance and power. Srinivasan stated that majority of power used is related to latches, including clocking and the leakage of power per latch. The number of latches grows super linearly with the number of pipeline stages according to Srinivasan. The overall power/performance is improved with the number of pipeline stages, as illustrated in the graph.

	[[File:~~Example~~.~~jpg~~]]		[[File:Pipeline_stage_vs_metric.png]]

	==Examples of Pipeline changes in Different Processors==		==Examples of Pipeline changes in Different Processors==

Bvuong: /* Power Consumption vs. Performance */

2013-09-17T16:22:52Z

Power Consumption vs. Performance

← Older revision		Revision as of 16:22, 17 September 2013
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	==Power Consumption vs. Performance==		==Power Consumption vs. Performance==
	Along with performance, power is another concern in microarchitectural design. There have been multiple studies on what optimal pipeline depth when considering both performance and power. Srinivasan stated that majority of power used is related to latches, including clocking and the leakage of power per latch. The number of latches grows super linearly with the number of pipeline stages according to Srinivasan. The overall power/performance is improved with the number of pipeline stages, as illustrated in the graph.		Along with performance, power is another concern in microarchitectural design. There have been multiple studies on what optimal pipeline depth when considering both performance and power. Srinivasan stated that majority of power used is related to latches, including clocking and the leakage of power per latch. The number of latches grows super linearly with the number of pipeline stages according to Srinivasan. The overall power/performance is improved with the number of pipeline stages, as illustrated in the graph.

			[[File:Example.jpg]]

	==Examples of Pipeline changes in Different Processors==		==Examples of Pipeline changes in Different Processors==

Bvuong: /* Power Consumption vs. Performance */

2013-09-17T16:22:14Z

Power Consumption vs. Performance

← Older revision		Revision as of 16:22, 17 September 2013
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	==Power Consumption vs. Performance==		==Power Consumption vs. Performance==
	Along with performance, power is another concern in microarchitectural design. There have been multiple studies on what optimal pipeline depth when considering both performance and power. Srinivasan stated that majority of power used is related to latches, including clocking and the leakage of power per latch. The number of latches grows super linearly with the number of pipeline stages according to Srinivasan.		Along with performance, power is another concern in microarchitectural design. There have been multiple studies on what optimal pipeline depth when considering both performance and power. Srinivasan stated that majority of power used is related to latches, including clocking and the leakage of power per latch. The number of latches grows super linearly with the number of pipeline stages according to Srinivasan. The overall power/performance is improved with the number of pipeline stages, as illustrated in the graph.

	==Examples of Pipeline changes in Different Processors==		==Examples of Pipeline changes in Different Processors==

Bvuong: /* Power Consumption vs. Performance */

2013-09-17T16:10:57Z

Power Consumption vs. Performance

← Older revision		Revision as of 16:10, 17 September 2013
Line 17:		Line 17:

	==Power Consumption vs. Performance==		==Power Consumption vs. Performance==
	Along with performance, power is another concern in microarchitectural design. There have been multiple studies on what optimal pipeline depth when considering both performance and power. Srinivasan stated that majority of power used is related to latches, including clocking and the leakage of power per latch. The number of latches grows super linearly with the number of pipeline stages according to Srinivasan,		Along with performance, power is another concern in microarchitectural design. There have been multiple studies on what optimal pipeline depth when considering both performance and power. Srinivasan stated that majority of power used is related to latches, including clocking and the leakage of power per latch. The number of latches grows super linearly with the number of pipeline stages according to Srinivasan.

	==Examples of Pipeline changes in Different Processors==		==Examples of Pipeline changes in Different Processors==

Weblazer: /* Sources */

2013-09-17T16:05:10Z

Sources

← Older revision		Revision as of 16:05, 17 September 2013
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	<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc The AMD Opteron Processor for Multiprocessor Servers] Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway </li>		<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc The AMD Opteron Processor for Multiprocessor Servers] Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway </li>
	<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1] Wikipedia</li>		<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1] Wikipedia</li>
	<li>[http://en.wikipedia.org/wiki/XK7 Cray ~~SK7~~] Wikipedia</li>		<li>[http://en.wikipedia.org/wiki/XK7 Cray XK7] Wikipedia</li>
	<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&ved=0CDkQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.93.4333%26rep%3Drep1%26type%3Dpdf&ei=BwwmUtX-D7OgsQSrxYCgDw&usg=AFQjCNFrDohjVe-SefuaJvLAJwXEFVgWYw&sig2=Hfx9Gs6MI8XtOVT3PvoDlw&bvm=bv.51495398,d.cWc The Optimum Pipeline Depth for a Microprocessor] A. Hartstein, Thomas R. Puzak</li>		<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&ved=0CDkQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.93.4333%26rep%3Drep1%26type%3Dpdf&ei=BwwmUtX-D7OgsQSrxYCgDw&usg=AFQjCNFrDohjVe-SefuaJvLAJwXEFVgWYw&sig2=Hfx9Gs6MI8XtOVT3PvoDlw&bvm=bv.51495398,d.cWc The Optimum Pipeline Depth for a Microprocessor] A. Hartstein, Thomas R. Puzak</li>
	<li>[http://www.readcube.com/articles/10.1002/ecjc.20127?locale=en An Analysis about Increasable Latch Overheard time for Processor Pipeline Depth Increase] Magoshi & Murakami</li>		<li>[http://www.readcube.com/articles/10.1002/ecjc.20127?locale=en An Analysis about Increasable Latch Overheard time for Processor Pipeline Depth Increase] Magoshi & Murakami</li>
	<li>[http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture] Dr.Thomas Chen, Dr.Ram Raghavan, Jason Dale, Eiji Iwata</li>		<li>[http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture] Dr.Thomas Chen, Dr.Ram Raghavan, Jason Dale, Eiji Iwata</li>
	</ol>		</ol>

Weblazer: /* Sources */

2013-09-17T16:04:43Z

Sources

← Older revision		Revision as of 16:04, 17 September 2013
Line 51:		Line 51:
	<ol>		<ol>
	<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc The AMD Opteron Processor for Multiprocessor Servers] Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway </li>		<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc The AMD Opteron Processor for Multiprocessor Servers] Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway </li>
	<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1]</li>		<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1] Wikipedia</li>
	<li>[http://en.wikipedia.org/wiki/XK7 Cray SK7]</li>		<li>[http://en.wikipedia.org/wiki/XK7 Cray SK7] Wikipedia</li>
	<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&ved=0CDkQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.93.4333%26rep%3Drep1%26type%3Dpdf&ei=BwwmUtX-D7OgsQSrxYCgDw&usg=AFQjCNFrDohjVe-SefuaJvLAJwXEFVgWYw&sig2=Hfx9Gs6MI8XtOVT3PvoDlw&bvm=bv.51495398,d.cWc The Optimum Pipeline Depth for a Microprocessor] A. Hartstein, Thomas R. Puzak</li>		<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&ved=0CDkQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.93.4333%26rep%3Drep1%26type%3Dpdf&ei=BwwmUtX-D7OgsQSrxYCgDw&usg=AFQjCNFrDohjVe-SefuaJvLAJwXEFVgWYw&sig2=Hfx9Gs6MI8XtOVT3PvoDlw&bvm=bv.51495398,d.cWc The Optimum Pipeline Depth for a Microprocessor] A. Hartstein, Thomas R. Puzak</li>
	<li>[http://www.readcube.com/articles/10.1002/ecjc.20127?locale=en An Analysis about Increasable Latch Overheard time for Processor Pipeline Depth Increase] Magoshi & Murakami</li>		<li>[http://www.readcube.com/articles/10.1002/ecjc.20127?locale=en An Analysis about Increasable Latch Overheard time for Processor Pipeline Depth Increase] Magoshi & Murakami</li>
	<li>[http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture] Dr.Thomas Chen, Dr.Ram Raghavan, Jason Dale, Eiji Iwata</li>		<li>[http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture] Dr.Thomas Chen, Dr.Ram Raghavan, Jason Dale, Eiji Iwata</li>
	</ol>		</ol>

Weblazer: /* Sources */

2013-09-17T16:04:18Z

Sources

← Older revision		Revision as of 16:04, 17 September 2013
Line 50:		Line 50:
	==Sources==		==Sources==
	<ol>		<ol>
	<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc The AMD Opteron Processor for Multiprocessor Servers ] Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway </li>		<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc The AMD Opteron Processor for Multiprocessor Servers] Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway </li>
	<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1]</li>		<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1]</li>
	<li>[http://en.wikipedia.org/wiki/XK7 Cray SK7]</li>		<li>[http://en.wikipedia.org/wiki/XK7 Cray SK7]</li>

Weblazer: /* Sources */

2013-09-17T16:04:02Z

Sources

← Older revision		Revision as of 16:04, 17 September 2013
Line 50:		Line 50:
	==Sources==		==Sources==
	<ol>		<ol>
	<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc The AMD Opteron Processor for Multiprocessor Servers ]</li>		<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc The AMD Opteron Processor for Multiprocessor Servers ] Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway </li>
	<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1]</li>		<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1]</li>
	<li>[http://en.wikipedia.org/wiki/XK7 Cray SK7]</li>		<li>[http://en.wikipedia.org/wiki/XK7 Cray SK7]</li>

Weblazer: /* Examples of Pipeline changes in Different Processors */

2013-09-17T16:02:32Z

Examples of Pipeline changes in Different Processors

← Older revision		Revision as of 16:02, 17 September 2013
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	\|2006		\|2006
	\|IBM Cell BE		\|IBM Cell BE
	\|23 [7]		\|23 [6]
	\|16		\|16
	\|-		\|-

Weblazer: /* Sources */

2013-09-17T16:02:21Z

Sources

← Older revision		Revision as of 16:02, 17 September 2013
Line 53:		Line 53:
	<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1]</li>		<li>[http://en.wikipedia.org/wiki/Cray-1 Cray 1]</li>
	<li>[http://en.wikipedia.org/wiki/XK7 Cray SK7]</li>		<li>[http://en.wikipedia.org/wiki/XK7 Cray SK7]</li>
	<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&ved=0CDkQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.93.4333%26rep%3Drep1%26type%3Dpdf&ei=BwwmUtX-D7OgsQSrxYCgDw&usg=AFQjCNFrDohjVe-SefuaJvLAJwXEFVgWYw&sig2=Hfx9Gs6MI8XtOVT3PvoDlw&bvm=bv.51495398,d.cWc The Optimum Pipeline Depth for a Microprocessor]</li>		<li>[https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&ved=0CDkQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.93.4333%26rep%3Drep1%26type%3Dpdf&ei=BwwmUtX-D7OgsQSrxYCgDw&usg=AFQjCNFrDohjVe-SefuaJvLAJwXEFVgWYw&sig2=Hfx9Gs6MI8XtOVT3PvoDlw&bvm=bv.51495398,d.cWc The Optimum Pipeline Depth for a Microprocessor] A. Hartstein, Thomas R. Puzak</li>
	<li>[http://www.readcube.com/articles/10.1002/ecjc.20127?locale=en An Analysis about Increasable Latch Overheard time for Processor Pipeline Depth Increase] Magoshi & Murakami</li>		<li>[http://www.readcube.com/articles/10.1002/ecjc.20127?locale=en An Analysis about Increasable Latch Overheard time for Processor Pipeline Depth Increase] Magoshi & Murakami</li>
	~~<li>[http://dl.acm.org/citation.cfm?id=956566 Optimum Power/Performance Pipeline Depth] A. Hartstein, Thomas R. Puzak</li>~~
	<li>[http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture] Dr.Thomas Chen, Dr.Ram Raghavan, Jason Dale, Eiji Iwata</li>		<li>[http://www.ibm.com/developerworks/power/library/pa-cellperf/ Cell Broadband Engine Architecture] Dr.Thomas Chen, Dr.Ram Raghavan, Jason Dale, Eiji Iwata</li>
	</ol>		</ol>