CSC/ECE 506 Spring 2015/8a ds - Revision history

Admin: /* Real Architectures using MSI */

2015-04-03T17:30:49Z

Real Architectures using MSI

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	==Real Architectures using MSI==		==Real Architectures using MSI==
	'''[http://en.wikipedia.org/wiki/MSI_protocol MSI]''' protocol was first used in '''[http://en.wikipedia.org/wiki/Silicon_Graphics SGI]''' IRIS 4D series. '''[http://en.wikipedia.org/wiki/Silicon_Graphics SGI]''' produced a broad range of '''[http://en.wikipedia.org/wiki/MIPS_architecture MIPS]'''-based (Microprocessor without Interlocked Pipeline Stages) workstations and servers during the 1990s, running '''[http://en.wikipedia.org/wiki/Silicon_Graphics SGI]''''s version of UNIX System V, now called '''[http://en.wikipedia.org/wiki/IRIX IRIX]'''. The 4D-MP graphics superworkstation brought 40 MIPS(million instructions per second) of computing performance to a graphics superworkstation. The unprecedented level of computing and graphics processing in an office-environment workstation was made possible by the fastest available RISC microprocessors in a single shared memory multiprocessor design driving a tightly coupled and highly parallel graphics system. Aggregate sustained data rates of over one gigabyte per second were achieved by a hierarchy of buses in a balanced system designed to avoid bottlenecks.		'''[http://en.wikipedia.org/wiki/MSI_protocol MSI]''' protocol was first used in '''[http://en.wikipedia.org/wiki/Silicon_Graphics SGI]''' IRIS 4D series. '''[http://en.wikipedia.org/wiki/Silicon_Graphics SGI]''' produced a broad range of '''[http://en.wikipedia.org/wiki/MIPS_architecture MIPS]'''-based (Microprocessor without Interlocked Pipeline Stages) workstations and servers during the 1990s, running '''[http://en.wikipedia.org/wiki/Silicon_Graphics SGI]''''s version of UNIX System V, now called '''[http://en.wikipedia.org/wiki/IRIX IRIX]'''. The 4D-MP graphics superworkstation brought 40 MIPS (million instructions per second) of computing performance to a graphics superworkstation. The unprecedented level of computing and graphics processing in an office-environment workstation was made possible by the fastest available RISC microprocessors in a single shared memory multiprocessor design driving a tightly coupled and highly parallel graphics system. Aggregate sustained data rates of over one gigabyte per second were achieved by a hierarchy of buses in a balanced system designed to avoid bottlenecks.

	The multiprocessor bus used in 4D-MP graphics superworkstation is a pipelined, block transfer bus that supports the cache coherence protocol as well as providing 64 megabytes of sustained data bandwidth between the processors, the memory and I/O system and the graphics subsystem. Since the sync bus provides for efficient synchronization between processors, the cache coherence protocol was designed to support efficient data sharing between processors. If a cache coherence protocol has to support synchronization as well as sharing, a compromise in the efficiency of the data sharing protocol may be necessary to improve the efficiency of the synchronization operations. Hence it uses the simple cache coherence protocol which is the '''[http://en.wikipedia.org/wiki/MSI_protocol MSI]''' protocol.		The multiprocessor bus used in 4D-MP graphics superworkstation is a pipelined, block transfer bus that supports the cache coherence protocol as well as providing 64 megabytes of sustained data bandwidth between the processors, the memory and I/O system and the graphics subsystem. Since the sync bus provides for efficient synchronization between processors, the cache coherence protocol was designed to support efficient data sharing between processors. If a cache coherence protocol has to support synchronization as well as sharing, a compromise in the efficiency of the data sharing protocol may be necessary to improve the efficiency of the synchronization operations. Hence it uses the simple cache coherence protocol which is the '''[http://en.wikipedia.org/wiki/MSI_protocol MSI]''' protocol.

Admin at 17:22, 3 April 2015

2015-04-03T17:22:12Z

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	== MSI, MESI, MESIF, and MOESI protocols on real architectures ==		= MSI, MESI, MESIF, and MOESI protocols on real architectures =
	Writeup:https://docs.google.com/document/d/1wVsWId15M0czXs4-9zu7D65UdQy38hK8xfcle9bft7s/edit#		Writeup:https://docs.google.com/document/d/1wVsWId15M0czXs4-9zu7D65UdQy38hK8xfcle9bft7s/edit#
	<br>		<br>

Admin at 17:21, 3 April 2015

2015-04-03T17:21:46Z

← Older revision		Revision as of 17:21, 3 April 2015
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			== MSI, MESI, MESIF, and MOESI protocols on real architectures ==
	Writeup:https://docs.google.com/document/d/1wVsWId15M0czXs4-9zu7D65UdQy38hK8xfcle9bft7s/edit#		Writeup:https://docs.google.com/document/d/1wVsWId15M0czXs4-9zu7D65UdQy38hK8xfcle9bft7s/edit#
	<br>		<br>

Dhupadhy: /* MSI Protocol */

2015-03-23T22:24:59Z

MSI Protocol

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	<br>In MSI protocol Bus-side requests include:		<br>In MSI protocol Bus-side requests include:
	*'''BusRd''': BusRd transaction is generated by a PrRd that misses in the cache, and the processor expects a data response as a result. The cache controller puts the address on the bus and asks for a copy that it does not intend to modify. The memory supplies the data, but when the corresponding block is present in a cache in M state then the processor flushes the data to the requester.		*'''BusRd''': BusRd transaction is generated by a PrRd that misses in the cache, and the processor expects a data response as a result. The cache controller puts the address on the bus and asks for a copy that it does not intend to modify. The memory supplies the data, but when the corresponding block is present in a cache in M state then the processor flushes the data to the requester.
			[[File:StateDiagramwithupgr.png\|600px\|thumbnail\|State transition diagram for MSI protocol with BusUpgr]]
	*'''BusRdX''': BusRdX transaction is generated by a PrWr to a block that is either not in the cache or is in the cache but is not in modified state. The cache controller puts the address on the bus and asks for an exclusive copy that it intends to modify. The memory system provides the data. All other caches are invalidated. Once the cache obtains the exclusive copy, the write can be performed in the cache.		*'''BusRdX''': BusRdX transaction is generated by a PrWr to a block that is either not in the cache or is in the cache but is not in modified state. The cache controller puts the address on the bus and asks for an exclusive copy that it intends to modify. The memory system provides the data. All other caches are invalidated. Once the cache obtains the exclusive copy, the write can be performed in the cache.
	*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.		*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.
	*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.		*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.
	~~[[File:StateDiagramwithupgr.png\|600px\|thumbnail\|State transition diagram for MSI protocol with BusUpgr]]~~
	<br>		<br><br><br><br><br><br>
	The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>		The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>
	[[File:MSI-states.jpg\|550px]]<br>		[[File:MSI-states.jpg\|550px]]<br>

Dhupadhy: /* MSI Protocol */

2015-03-23T22:21:46Z

MSI Protocol

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	*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.		*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.
	*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.		*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.
	[[File:StateDiagramwithupgr.png\|~~right~~\|State transition diagram for MSI protocol with BusUpgr]]		[[File:StateDiagramwithupgr.png\|600px\|thumbnail\|State transition diagram for MSI protocol with BusUpgr]]
	<br>		<br>
	The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>		The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>

Dhupadhy: /* MSI Protocol */

2015-03-23T22:19:36Z

MSI Protocol

← Older revision		Revision as of 22:19, 23 March 2015
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	*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.		*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.
	*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.		*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.
			[[File:StateDiagramwithupgr.png\|right\|State transition diagram for MSI protocol with BusUpgr]]
	<br>		<br>
	The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>		The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>

Dhupadhy: /* MSI Protocol */

2015-03-23T22:05:26Z

MSI Protocol

← Older revision		Revision as of 22:05, 23 March 2015
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	*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.		*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.
	*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.		*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.
	~~[[File:Busupgrade.png\|600px\|thumbnail\|State transition diagram for MSI protocol with BusUpgr]]~~
	<br>		<br>
	The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>		The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>

Dhupadhy: /* MSI Protocol */

2015-03-23T22:03:53Z

MSI Protocol

← Older revision		Revision as of 22:03, 23 March 2015
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	*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.		*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.
	*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.		*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.
	[[File:~~BusUpgr~~.png\|600px\|thumbnail\|State transition diagram for MSI protocol with BusUpgr]]		[[File:Busupgrade.png\|600px\|thumbnail\|State transition diagram for MSI protocol with BusUpgr]]
	<br>		<br>
	The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>		The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>

Dhupadhy: /* MSI Protocol */

2015-03-23T22:02:56Z

MSI Protocol

← Older revision		Revision as of 22:02, 23 March 2015
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	*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.		*'''Flush''': Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.
	*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.		*'''BusUpgr''': snooped request that indicates that there is a write request to a cache block that another processor already has in its cache.
			[[File:BusUpgr.png\|600px\|thumbnail\|State transition diagram for MSI protocol with BusUpgr]]
	<br>		<br>
	The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>		The MSI states under different conditions are shown below:<ref>[http://www.cs.utah.edu/formal_verification/pdf/xiaofang_dissertation.pdf Verification of Hierarchical Cache Coherence Protocols for Futuristic Processors]</ref><br>

Dhupadhy: /* MSI Protocol */

2015-03-23T21:44:33Z

MSI Protocol

← Older revision		Revision as of 21:44, 23 March 2015
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	= MSI Protocol =		= MSI Protocol =
	[http://www.scribd.com/doc/50676653/19/MSI-protocol MSI] protocol is a three-state write-back invalidation protocol which is one of the simplest and earliest-used snooping-based cache coherence-protocols. According to this protocol, a cache block can be in one of the following three states: Modified (M), Shared (S) or Invalid (I). MSI protocol can be implemented with or without the Bus Upgrade feature. The memory controller responds differently to the BusRdx operation and the BusUpgr operation. If BusRdx is snooped, the memory controller fetches the block. When BusUpgr is snooped, the memory controller ignores it and doesn't perform a fetch. Therefore, by implementing the protocol with BusUpgr, memory traffic can be reduced.		[http://www.scribd.com/doc/50676653/19/MSI-protocol MSI] protocol is a three-state write-back invalidation protocol which is one of the simplest and earliest-used snooping-based cache coherence-protocols. According to this protocol, a cache block can be in one of the following three states: Modified (M), Shared (S) or Invalid (I). MSI protocol can be implemented with or without the Bus Upgrade feature. The memory controller responds differently to the BusRdx operation and the BusUpgr operation. If BusRdx is snooped, the memory controller fetches the block. When BusUpgr is snooped, the memory controller ignores it and doesn't perform a fetch. Therefore, by implementing the protocol with BusUpgr, memory traffic can be reduced.
	[[File:MSInew.jpg\|600px\|thumbnail\|State transition diagram for MSI protocol]]		[[File:MSInew.jpg\|600px\|thumbnail\|State transition diagram for MSI protocol without BusUpgr]]
	*'''Modified''' state indicates that the variable in the cache has been modified and therefore has a different value from that found in the main memory. A cache line in this state thus needs to be written back to memory during eviction. Only one of the processors can have the cache block in Modified state at a time.		*'''Modified''' state indicates that the variable in the cache has been modified and therefore has a different value from that found in the main memory. A cache line in this state thus needs to be written back to memory during eviction. Only one of the processors can have the cache block in Modified state at a time.
	*'''Shared''' state indicates that the block exists in one or more caches, and is clean, implying that its value is consistent with the one in main memory. So a cache block in this state can be evicted without having to write it back to the main memory.		*'''Shared''' state indicates that the block exists in one or more caches, and is clean, implying that its value is consistent with the one in main memory. So a cache block in this state can be evicted without having to write it back to the main memory.