CSC/ECE 506 Spring 2014/7b ss - Revision history

Sjantli: /* Validation Based Approach */

2014-03-25T01:28:17Z

Validation Based Approach

← Older revision		Revision as of 01:28, 25 March 2014
Line 159:		Line 159:
	Under this approach, TLB invalidation is postponed until memory is accessed. This approach eliminates the need for interrupts and synchronization. Validation table has mapping of frame and the latest count. When a processor sends a memory requests, the requests also contains the generation count which is stored in the processor’s TLB. If the count in the request and validation table is matched, then the access is granted else the TLB entry of that processor is invalidated.<ref>[http://www.cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf "Teller, Patricia J. Translation-Lookaside Buffer Consistency"]		Under this approach, TLB invalidation is postponed until memory is accessed. This approach eliminates the need for interrupts and synchronization. Validation table has mapping of frame and the latest count. When a processor sends a memory requests, the requests also contains the generation count which is stored in the processor’s TLB. If the count in the request and validation table is matched, then the access is granted else the TLB entry of that processor is invalidated.<ref>[http://www.cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf "Teller, Patricia J. Translation-Lookaside Buffer Consistency"]
	</ref>		</ref>

	~~[[File: Vba.png‎\|400px\|thumb\|right\| Validation based approach (Source-Translation-Lookaside Buffer Consistency Patricia J. Teller IBM Thomas J. Watson Research Center)]]~~

	=== Modified TLB Shootdown ===		=== Modified TLB Shootdown ===

Sjantli: /* Quiz */

2014-03-25T01:26:28Z

Quiz

@@ Line 322: / Line 322: @@
 ::c) Via a hardware instruction
 ::d) Via a lock to the page table in main memory
 Answers
--a, 2-a, 3-a, 4-c, 5-a,b,c,d, 6-c, 7-a,b, 8-b, 9-d, 10-d
+-a, 2-a, 3-a, 4-c, 5-a,b,c,d, 6-c, 7-a,b, 8-b, 9-d, 10-d 11-a 12-b

Sjantli: /* Definitions */

2014-03-25T01:09:47Z

Definitions

← Older revision		Revision as of 01:09, 25 March 2014
Line 219:		Line 219:
	;Safe Change		;Safe Change
	: A type of update that can be made to a PMT safely without also updating the cached TLB counterpart.		: A type of update that can be made to a PMT safely without also updating the cached TLB counterpart.

			;Unsafe Change
			: The change that will cause TLB coherence problem.

	;TLB Coherence Strategy		;TLB Coherence Strategy

Sjantli: /* Definitions */

2014-03-25T01:08:34Z

Definitions

← Older revision		Revision as of 01:08, 25 March 2014
Line 232:		Line 232:
	: A number assigned to process that is unique within the scope of a processor for a specified time period. A process may be assigned multiple ASIDs across time. Used with the TLB entries, the ASID helps the discard stale TLB entries.		: A number assigned to process that is unique within the scope of a processor for a specified time period. A process may be assigned multiple ASIDs across time. Used with the TLB entries, the ASID helps the discard stale TLB entries.

	;~~Hierarchical~~ TLBs		;Modified TLB Shootdown
	: ~~Is analogus concept for TLBS as multilevel L1 and L2 cache~~		: Busy waiting for synchronization with other processors while using page table is avoided.

			;Read Locked TLBs
			: Does not allow unsafe changes to be done if valid copy exists in more than one TLB.

	;Page Table Base Register		;Page Table Base Register

Sjantli: /* Unified Cache and TLB coherence solution */

2014-03-25T00:59:59Z

Unified Cache and TLB coherence solution

← Older revision		Revision as of 00:59, 25 March 2014
Line 202:		Line 202:

	PCAM entries are removed as a result of the replacement of the corresponding translation in the TLB or due to an incoming coherence request for read-write access. If a coherence request hits in the PCAM, the Valid bit for the corresponding TLB entry is cleared. If multiple TLB translations have the same PTE block address, a PCAM lookup on this block address results in the identification of all associated TLB entries. Figure 2(b) above illustrates a coherence invalidation of physical address 12 that hits in two PCAM entries.		PCAM entries are removed as a result of the replacement of the corresponding translation in the TLB or due to an incoming coherence request for read-write access. If a coherence request hits in the PCAM, the Valid bit for the corresponding TLB entry is cleared. If multiple TLB translations have the same PTE block address, a PCAM lookup on this block address results in the identification of all associated TLB entries. Figure 2(b) above illustrates a coherence invalidation of physical address 12 that hits in two PCAM entries.

	~~=== Performance ===~~
	The performance of the UNITD protocol is compared to a) a baseline system that relies on TLB shootdowns and b) to a system with ideal (zero-latency) translation invalidations. (The ideal-invalidation system uses the same modified OS as UNITD (i.e., with no TLB shootdown support) and verifies that a translation is coherent whenever it is accessed in the TLB. The validation
	~~is done in the background and has no performance impact).~~

	UNITD is efficient in ensuring translation coherence, as it performs as well as the system with ideal TLB invalidations. UNITD speedups increase with the number of TLB shootdowns and with the number of cores. Third, as expected, UNITD has no impact on performance in the absence of TLB shootdowns. (Refer to the graph below).

	~~[[File:TLBFigure7.png\|frame\|none\|alt=alt text\|Figure 5: (Source-UNITD protocol paper by Romanescu/Lebeck/Sorin/Bracy) single_unmap benchmark. UNITD speedup over baseline system for directory.]]~~

	== Definitions ==		== Definitions ==

Sjantli: /* Validation Based Approach */

2014-03-25T00:47:19Z

Validation Based Approach

← Older revision		Revision as of 00:47, 25 March 2014
Line 159:		Line 159:
	Under this approach, TLB invalidation is postponed until memory is accessed. This approach eliminates the need for interrupts and synchronization. Validation table has mapping of frame and the latest count. When a processor sends a memory requests, the requests also contains the generation count which is stored in the processor’s TLB. If the count in the request and validation table is matched, then the access is granted else the TLB entry of that processor is invalidated.<ref>[http://www.cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf "Teller, Patricia J. Translation-Lookaside Buffer Consistency"]		Under this approach, TLB invalidation is postponed until memory is accessed. This approach eliminates the need for interrupts and synchronization. Validation table has mapping of frame and the latest count. When a processor sends a memory requests, the requests also contains the generation count which is stored in the processor’s TLB. If the count in the request and validation table is matched, then the access is granted else the TLB entry of that processor is invalidated.<ref>[http://www.cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf "Teller, Patricia J. Translation-Lookaside Buffer Consistency"]
	</ref>		</ref>

			[[File: Vba.png‎\|400px\|thumb\|right\| Validation based approach (Source-Translation-Lookaside Buffer Consistency Patricia J. Teller IBM Thomas J. Watson Research Center)]]

	=== Modified TLB Shootdown ===		=== Modified TLB Shootdown ===

Sjantli: Undo revision 84030 by Sjantli (talk)

2014-03-25T00:46:32Z

Undo revision 84030 by Sjantli (talk)

← Older revision		Revision as of 00:46, 25 March 2014
Line 159:		Line 159:
	Under this approach, TLB invalidation is postponed until memory is accessed. This approach eliminates the need for interrupts and synchronization. Validation table has mapping of frame and the latest count. When a processor sends a memory requests, the requests also contains the generation count which is stored in the processor’s TLB. If the count in the request and validation table is matched, then the access is granted else the TLB entry of that processor is invalidated.<ref>[http://www.cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf "Teller, Patricia J. Translation-Lookaside Buffer Consistency"]		Under this approach, TLB invalidation is postponed until memory is accessed. This approach eliminates the need for interrupts and synchronization. Validation table has mapping of frame and the latest count. When a processor sends a memory requests, the requests also contains the generation count which is stored in the processor’s TLB. If the count in the request and validation table is matched, then the access is granted else the TLB entry of that processor is invalidated.<ref>[http://www.cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf "Teller, Patricia J. Translation-Lookaside Buffer Consistency"]
	</ref>		</ref>

	~~[[File: vba.png‎\|400px\|thumb\|right\| Validation based approach (Source-Translation-Lookaside Buffer Consistency Patricia J. Teller IBM Thomas J. Watson Research Center)]]~~

	=== Modified TLB Shootdown ===		=== Modified TLB Shootdown ===

Sjantli at 00:45, 25 March 2014

2014-03-25T00:45:19Z

← Older revision		Revision as of 00:45, 25 March 2014
Line 159:		Line 159:
	Under this approach, TLB invalidation is postponed until memory is accessed. This approach eliminates the need for interrupts and synchronization. Validation table has mapping of frame and the latest count. When a processor sends a memory requests, the requests also contains the generation count which is stored in the processor’s TLB. If the count in the request and validation table is matched, then the access is granted else the TLB entry of that processor is invalidated.<ref>[http://www.cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf "Teller, Patricia J. Translation-Lookaside Buffer Consistency"]		Under this approach, TLB invalidation is postponed until memory is accessed. This approach eliminates the need for interrupts and synchronization. Validation table has mapping of frame and the latest count. When a processor sends a memory requests, the requests also contains the generation count which is stored in the processor’s TLB. If the count in the request and validation table is matched, then the access is granted else the TLB entry of that processor is invalidated.<ref>[http://www.cs.uwaterloo.ca/~brecht/courses/702/Possible-Readings/multiprocessor/tlb-consistency-computer-1990.pdf "Teller, Patricia J. Translation-Lookaside Buffer Consistency"]
	</ref>		</ref>

			[[File: vba.png‎\|400px\|thumb\|right\| Validation based approach (Source-Translation-Lookaside Buffer Consistency Patricia J. Teller IBM Thomas J. Watson Research Center)]]

	=== Modified TLB Shootdown ===		=== Modified TLB Shootdown ===

Smeenak3 at 00:38, 25 March 2014

2014-03-25T00:38:17Z

← Older revision		Revision as of 00:38, 25 March 2014
Line 160:		Line 160:
	</ref>		</ref>

	~~[[File: vba.png‎\|400px\|thumb\|right\| Validation based approach (Source-Translation-Lookaside Buffer Consistency Patricia J. Teller IBM Thomas J. Watson Research Center)]]~~
	=== Modified TLB Shootdown ===		=== Modified TLB Shootdown ===

Smeenak3 at 00:31, 25 March 2014

2014-03-25T00:31:19Z

← Older revision		Revision as of 00:31, 25 March 2014
Line 160:		Line 160:
	</ref>		</ref>

			[[File: vba.png‎\|400px\|thumb\|right\| Validation based approach (Source-Translation-Lookaside Buffer Consistency Patricia J. Teller IBM Thomas J. Watson Research Center)]]
	=== Modified TLB Shootdown ===		=== Modified TLB Shootdown ===