CSC/ECE 506 Spring 2013/8b ap - Revision history

Pnaraya4: /* Write Back Write Invalidate caches */

2013-03-27T18:43:08Z

Write Back Write Invalidate caches

← Older revision		Revision as of 18:43, 27 March 2013
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	[[File:wiki_invalidate_states.jpg‎]]<br />		[[File:wiki_invalidate_states.jpg‎]]<br />
	'''Figure 1. Write-through Write Invalidate States'''		'''Figure 1. Write-through Write Invalidate States Bus Snooping Protocol'''

2013-03-27T18:42:11Z

Write-Through Write Invalidate Caches

← Older revision		Revision as of 18:42, 27 March 2013
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	[[File:Wiki_invalidate_bus.jpg‎]]<br />		[[File:Wiki_invalidate_bus.jpg‎]]<br />
	'''Figure 1. Write-through Write Invalidate ~~Bus Snooping Protocol~~'''		'''Figure 1. Write-through Write Invalidate'''

	==== Advantages ====		==== Advantages ====

2013-03-27T18:41:39Z

Write Back Write Invalidate caches

← Older revision		Revision as of 18:41, 27 March 2013
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	• Bus Transactions		• Bus Transactions
	Bus Read (BusRd), Write-Back (BusWB)		Bus Read (BusRd), Write-Back (BusWB)


			[[File:wiki_invalidate_states.jpg‎]]<br />
			'''Figure 1. Write-through Write Invalidate States'''



	==== Write-through Advantages : ====		==== Write-through Advantages : ====

2013-03-27T18:41:20Z

Write-Through Write Invalidate Caches

← Older revision		Revision as of 18:41, 27 March 2013
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	On a BusRd, a cache block in the valid state remains in the valid state. While a block in the invalid state remains in the invalid state.		On a BusRd, a cache block in the valid state remains in the valid state. While a block in the invalid state remains in the invalid state.
	On a BusWr, a cache block in the valid state gets into the invalid state and an invalid block remain in the invalid state.		On a BusWr, a cache block in the valid state gets into the invalid state and an invalid block remain in the invalid state.

	~~[[File:wiki_invalidate_states.jpg‎]]<br />~~
	~~'''Figure 1. Write-through Write Invalidate States'''~~

	[[File:Wiki_invalidate_bus.jpg‎]]<br />		[[File:Wiki_invalidate_bus.jpg‎]]<br />

2013-03-27T18:40:34Z

Write-Through Write Invalidate Caches

← Older revision		Revision as of 18:40, 27 March 2013
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	On a BusRd, a cache block in the valid state remains in the valid state. While a block in the invalid state remains in the invalid state.		On a BusRd, a cache block in the valid state remains in the valid state. While a block in the invalid state remains in the invalid state.
	On a BusWr, a cache block in the valid state gets into the invalid state and an invalid block remain in the invalid state.		On a BusWr, a cache block in the valid state gets into the invalid state and an invalid block remain in the invalid state.

			[[File:wiki_invalidate_states.jpg‎]]<br />
			'''Figure 1. Write-through Write Invalidate States'''

			[[File:Wiki_invalidate_bus.jpg‎]]<br />
			'''Figure 1. Write-through Write Invalidate Bus Snooping Protocol'''

	==== Advantages ====		==== Advantages ====

2013-03-27T18:22:24Z

Write Back Write Invalidate caches

← Older revision		Revision as of 18:22, 27 March 2013
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	Bus Read (BusRd), Write-Back (BusWB)		Bus Read (BusRd), Write-Back (BusWB)

	Write-through Advantages :		==== Write-through Advantages : ====
	When a processor continuously writes into the same cache block, only a single command is used to invalidate the cache blocks		When a processor continuously writes into the same cache block, only a single command is used to invalidate the cache blocks
	Disadvantage :		==== Disadvantage : ====
	requires a high amount of bandwidth.		requires a high amount of bandwidth.

2013-03-27T18:20:28Z

Cache Coherence Protocols on Real Architectures

← Older revision		Revision as of 18:20, 27 March 2013
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	[[File:~~Wiki_first_shared~~.~~jpg‎~~]]<br />		[[File:Shared memory.png‎]]<br />
	'''Figure 1. Multiple Caches of Shared Resource'''		'''Figure 1. Multiple Caches of Shared Resource'''

2013-03-27T18:14:48Z

Cache Coherence Protocols on Real Architectures

← Older revision		Revision as of 18:14, 27 March 2013
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	[[File:~~Shared memory~~.~~jpg~~]]<br />		[[File:Wiki_first_shared.jpg‎]]<br />
	'''Figure 1. Multiple Caches of Shared Resource'''		'''Figure 1. Multiple Caches of Shared Resource'''

2013-03-21T18:32:57Z

Cache Coherence Protocols on Real Architectures

← Older revision		Revision as of 18:32, 21 March 2013
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	[[File:Shared memory.jpg]]		[[File:Shared memory.jpg]]<br />
	'''Figure 1. Multiple Caches of Shared Resource'''		'''Figure 1. Multiple Caches of Shared Resource'''

2013-03-21T18:32:22Z

Cache Coherence Protocols on Real Architectures

← Older revision		Revision as of 18:32, 21 March 2013
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	[[File:Shared memory.jpg]]		[[File:Shared memory.jpg]]
	~~<center>~~ '''Figure 1. Multiple Caches of Shared Resource''' ~~</center>~~		'''Figure 1. Multiple Caches of Shared Resource'''