CSC/ECE 506 Spring 2013/6a cs - Revision history

Cthinkel: /* References */

2013-03-04T07:43:55Z

References

← Older revision		Revision as of 07:43, 4 March 2013
Line 295:		Line 295:
	<br />		<br />
	<span id="19foot">[[#19body\|19.]]</span> http://en.wikipedia.org/wiki/CPU_cache#History		<span id="19foot">[[#19body\|19.]]</span> http://en.wikipedia.org/wiki/CPU_cache#History
			<br />
	<span id="20foot">[[#20body\|20.]]</span> http://www.multicoreinfo.com/prefetching-multicore-processors/		<span id="20foot">[[#20body\|20.]]</span> http://www.multicoreinfo.com/prefetching-multicore-processors/

	<br />		<br />

	=Other References=		=Other References=
	<references/>		<references/>

Cthinkel: /* Prefetching */

2013-03-04T07:43:33Z

Prefetching

← Older revision		Revision as of 07:43, 4 March 2013
Line 158:		Line 158:
	Some architectures have instructions to prefetch data into cache. Programmers and compliers can insert this prefect instruction in the code. This is known as software prefetching. In hardware prefetching, processor observers the system behavior and issues requests for prefetching. Intel 8086 and Motorola 68000 were the first microprocessors to implement instruction prefetch. Graphics Processing Units benefit from prefetching due to spatial locality property of the data<sup><span id="8body">[[#8foot\|[8]]]</span></sup>.		Some architectures have instructions to prefetch data into cache. Programmers and compliers can insert this prefect instruction in the code. This is known as software prefetching. In hardware prefetching, processor observers the system behavior and issues requests for prefetching. Intel 8086 and Motorola 68000 were the first microprocessors to implement instruction prefetch. Graphics Processing Units benefit from prefetching due to spatial locality property of the data<sup><span id="8body">[[#8foot\|[8]]]</span></sup>.

	==Advantages== <sup><span id="20body">[[#20foot\|[20]]]</span></sup>		==Advantages==
	*Masks data access latency caused by cache misses.		*Masks data access latency caused by cache misses.<sup><span id="20body">[[#20foot\|[20]]]</span></sup>
	*Improves the performance between the processor and the memory.		*Improves the performance between the processor and the memory.<sup><span id="20body">[[#20foot\|[20]]]</span></sup>

	==Disadvantages==		==Disadvantages==

Cthinkel: /* Prefetching */

2013-03-04T07:43:18Z

Prefetching

← Older revision		Revision as of 07:43, 4 March 2013
Line 158:		Line 158:
	Some architectures have instructions to prefetch data into cache. Programmers and compliers can insert this prefect instruction in the code. This is known as software prefetching. In hardware prefetching, processor observers the system behavior and issues requests for prefetching. Intel 8086 and Motorola 68000 were the first microprocessors to implement instruction prefetch. Graphics Processing Units benefit from prefetching due to spatial locality property of the data<sup><span id="8body">[[#8foot\|[8]]]</span></sup>.		Some architectures have instructions to prefetch data into cache. Programmers and compliers can insert this prefect instruction in the code. This is known as software prefetching. In hardware prefetching, processor observers the system behavior and issues requests for prefetching. Intel 8086 and Motorola 68000 were the first microprocessors to implement instruction prefetch. Graphics Processing Units benefit from prefetching due to spatial locality property of the data<sup><span id="8body">[[#8foot\|[8]]]</span></sup>.

	==Advantages==<sup><span id="20body">[[#20foot\|[20]]]</span></sup>		==Advantages== <sup><span id="20body">[[#20foot\|[20]]]</span></sup>
	*Masks data access latency caused by cache misses.		*Masks data access latency caused by cache misses.
	*Improves the performance between the processor and the memory.		*Improves the performance between the processor and the memory.

Cthinkel at 07:43, 4 March 2013

2013-03-04T07:43:06Z

← Older revision		Revision as of 07:43, 4 March 2013
Line 158:		Line 158:
	Some architectures have instructions to prefetch data into cache. Programmers and compliers can insert this prefect instruction in the code. This is known as software prefetching. In hardware prefetching, processor observers the system behavior and issues requests for prefetching. Intel 8086 and Motorola 68000 were the first microprocessors to implement instruction prefetch. Graphics Processing Units benefit from prefetching due to spatial locality property of the data<sup><span id="8body">[[#8foot\|[8]]]</span></sup>.		Some architectures have instructions to prefetch data into cache. Programmers and compliers can insert this prefect instruction in the code. This is known as software prefetching. In hardware prefetching, processor observers the system behavior and issues requests for prefetching. Intel 8086 and Motorola 68000 were the first microprocessors to implement instruction prefetch. Graphics Processing Units benefit from prefetching due to spatial locality property of the data<sup><span id="8body">[[#8foot\|[8]]]</span></sup>.

	==Advantages==		==Advantages==<sup><span id="20body">[[#20foot\|[20]]]</span></sup>
	*Masks data access latency caused by cache misses.		*Masks data access latency caused by cache misses.
	*Improves the performance between the processor and the memory.		*Improves the performance between the processor and the memory.
Line 295:		Line 295:
	<br />		<br />
	<span id="19foot">[[#19body\|19.]]</span> http://en.wikipedia.org/wiki/CPU_cache#History		<span id="19foot">[[#19body\|19.]]</span> http://en.wikipedia.org/wiki/CPU_cache#History
			<span id="20foot">[[#20body\|20.]]</span> http://www.multicoreinfo.com/prefetching-multicore-processors/

	<br />		<br />
	=Other References=		=Other References=
	<references/>		<references/>

Cthinkel: /* Advantages */

2013-03-04T07:42:00Z

Advantages

← Older revision		Revision as of 07:42, 4 March 2013
Line 159:		Line 159:

	==Advantages==		==Advantages==
	*~~Improves overall performance~~ by ~~reducing~~ cache misses.		*Masks data access latency caused by cache misses.
			*Improves the performance between the processor and the memory.

	==Disadvantages==		==Disadvantages==
	* Wastes bandwidth when prefetched data is not used.		* Wastes bandwidth when prefetched data is not used.

Cthinkel: /* Prefetching */

2013-03-04T07:35:20Z

Prefetching

← Older revision		Revision as of 07:35, 4 March 2013
Line 155:		Line 155:

	=Prefetching=		=Prefetching=
	Prefetching is a technique that can be used in addition to write-hit and write-miss policies to improved the utilization of the cache. Microprocessors, such as those listed in Table 1, support prefetching logic directly in the chip. Cache is very efficient in terms on access time once that data or instructions are in the cache. But when a process tries to access something that is not already in the cache, a cache miss occurs and those pages need to be brought into the cache from memory. Generally cache miss are expensive to the performance as the processor has to wait for that data (In parallel processing, a process can execute other tasks while it is waiting on data, but there will be some overhead for this). Prefetching is a technique in which data is brought into cache before the program needs it. In other words, it is a way to reduce cache misses. Prefetching uses some type of prediction to mechanism to anticipate the next data that will be needed and brings them into cache. It is not guaranteed that the prefetched data will be used. Goal here is to reduce cache misses to improve overall performance.<br><br>		[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] is a technique that can be used in addition to write-hit and write-miss policies to improved the utilization of the cache. Microprocessors, such as those listed in Table 1, support prefetching logic directly in the chip. Cache is very efficient in terms on access time once that data or instructions are in the cache. But when a process tries to access something that is not already in the cache, a cache miss occurs and those pages need to be brought into the cache from memory. Generally cache miss are expensive to the performance as the processor has to wait for that data (In parallel processing, a process can execute other tasks while it is waiting on data, but there will be some overhead for this). Prefetching is a technique in which data is brought into cache before the program needs it. In other words, it is a way to reduce cache misses. Prefetching uses some type of prediction to mechanism to anticipate the next data that will be needed and brings them into cache. It is not guaranteed that the prefetched data will be used. Goal here is to reduce cache misses to improve overall performance.<br><br>
	Some architectures have instructions to prefetch data into cache. Programmers and compliers can insert this prefect instruction in the code. This is known as software prefetching. In hardware prefetching, processor observers the system behavior and issues requests for prefetching. Intel 8086 and Motorola 68000 were the first microprocessors to implement instruction prefetch. Graphics Processing Units benefit from prefetching due to spatial locality property of the data<sup><span id="8body">[[#8foot\|[8]]]</span></sup>.		Some architectures have instructions to prefetch data into cache. Programmers and compliers can insert this prefect instruction in the code. This is known as software prefetching. In hardware prefetching, processor observers the system behavior and issues requests for prefetching. Intel 8086 and Motorola 68000 were the first microprocessors to implement instruction prefetch. Graphics Processing Units benefit from prefetching due to spatial locality property of the data<sup><span id="8body">[[#8foot\|[8]]]</span></sup>.

Cthinkel: /* Cache Coherency protocol */

2013-03-04T07:34:12Z

Cache Coherency protocol

← Older revision		Revision as of 07:34, 4 March 2013
Line 265:		Line 265:

	==Cache Coherency protocol==		==Cache Coherency protocol==
	A '''coherency protocol''' is a protocol which maintains the consistency between all the caches in a system of [[distributed shared memory]]. The protocol maintains [[memory coherence]] according to a specific [[consistency model]]. Older multiprocessors support the [[sequential consistency]] model, while modern shared memory systems typically support the [[release consistency]] or [[weak consistency]] models.		A '''coherency protocol''' is a protocol which maintains the consistency between all the caches in a system of [http://en.wikipedia.org/wiki/Distributed_shared_memory distributed shared memory]. The protocol maintains [http://en.wikipedia.org/wiki/Memory_coherence memory coherence] according to a specific [http://en.wikipedia.org/wiki/Consistency_model consistency model]. Older multiprocessors support the [http://en.wikipedia.org/wiki/Sequential_consistency sequential consistency] model, while modern shared memory systems typically support the [http://en.wikipedia.org/wiki/Release_consistency release consistency] or [http://en.wikipedia.org/wiki/Weak_consistency weak consistency] models.

	Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.		Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.

Cthinkel: /* Cache Coherency protocol */

2013-03-04T07:32:39Z

Cache Coherency protocol

← Older revision		Revision as of 07:32, 4 March 2013
Line 269:		Line 269:
	Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.		Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.

	Various models and protocols have been devised for maintaining coherence, such as [http://en.wikipedia.org/wiki/MSI_protocol MSI], [http://en.wikipedia.org/wiki/MESI_protocol MESI] (aka Illinois), [http://en.wikipedia.org/wiki/MOSI_protocol MOSI], [http://en.wikipedia.org/wiki/MOESI_protocol MOESI], [http://en.wikipedia.org/wiki/MERSI_protocol MERSI], [http://en.wikipedia.org/wiki/MESIF_protocol MESIF], [http://en.wikipedia.org/wiki/Write-once_(cache_coherence) Write-once (cache coherence)], and [[Synapse ~~protocol\|Synapse]]~~, ~~[[Berkeley protocol\|~~Berkeley]], [http://en.wikipedia.org/wiki/Firefly_protocol Firefly] and [http://en.wikipedia.org/wiki/Dragon_protocol Dragon]'''.		Various models and protocols have been devised for maintaining coherence, such as [http://en.wikipedia.org/wiki/MSI_protocol MSI], [http://en.wikipedia.org/wiki/MESI_protocol MESI] (aka Illinois), [http://en.wikipedia.org/wiki/MOSI_protocol MOSI], [http://en.wikipedia.org/wiki/MOESI_protocol MOESI], [http://en.wikipedia.org/wiki/MERSI_protocol MERSI], [http://en.wikipedia.org/wiki/MESIF_protocol MESIF], [http://en.wikipedia.org/wiki/Write-once_(cache_coherence) Write-once (cache coherence)], and Synapse, Berkeley, [http://en.wikipedia.org/wiki/Firefly_protocol Firefly] and [http://en.wikipedia.org/wiki/Dragon_protocol Dragon]'''.

	=References=		=References=

Cthinkel: /* Cache Coherency protocol */

2013-03-04T07:32:08Z

Cache Coherency protocol

← Older revision		Revision as of 07:32, 4 March 2013
Line 269:		Line 269:
	Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.		Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.

	Various models and protocols have been devised for maintaining coherence, such as [http://en.wikipedia.org/wiki/MSI_protocol MSI], [http://en.wikipedia.org/wiki/MESI_protocol MESI] (aka Illinois), [http://en.wikipedia.org/wiki/MOSI_protocol MOSI], [http://en.wikipedia.org/wiki/MOESI_protocol MOESI], [http://en.wikipedia.org/wiki/MERSI_protocol MERSI], [http://en.wikipedia.org/wiki/MESIF_protocol MESIF], [http://en.wikipedia.org/wiki/Write-once_(cache_coherence) Write-once (cache coherence)], and [[Synapse protocol\|Synapse]], [[Berkeley protocol\|Berkeley]], [~~[Firefly protocol\|~~Firefly]] and [[Dragon ~~protocol]~~]'''.		Various models and protocols have been devised for maintaining coherence, such as [http://en.wikipedia.org/wiki/MSI_protocol MSI], [http://en.wikipedia.org/wiki/MESI_protocol MESI] (aka Illinois), [http://en.wikipedia.org/wiki/MOSI_protocol MOSI], [http://en.wikipedia.org/wiki/MOESI_protocol MOESI], [http://en.wikipedia.org/wiki/MERSI_protocol MERSI], [http://en.wikipedia.org/wiki/MESIF_protocol MESIF], [http://en.wikipedia.org/wiki/Write-once_(cache_coherence) Write-once (cache coherence)], and [[Synapse protocol\|Synapse]], [[Berkeley protocol\|Berkeley]], [http://en.wikipedia.org/wiki/Firefly_protocol Firefly] and [http://en.wikipedia.org/wiki/Dragon_protocol Dragon]'''.

	=References=		=References=

Cthinkel at 07:31, 4 March 2013

2013-03-04T07:31:18Z

← Older revision		Revision as of 07:31, 4 March 2013
Line 269:		Line 269:
	Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.		Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.

	Various models and protocols have been devised for maintaining coherence, such as [[MSI_protocol\|MSI]], [[MESI_protocol\|MESI]] (aka Illinois), [[MOSI_protocol\|MOSI]], [[MOESI_protocol\|MOESI]], [[MERSI_protocol\|MERSI]], [[MESIF_protocol\|MESIF]], [[Write-once (cache coherence)~~\|write-once]~~], and [[Synapse protocol\|Synapse]], [[Berkeley protocol\|Berkeley]], [[Firefly protocol\|Firefly]] and [[Dragon protocol]]'''.		Various models and protocols have been devised for maintaining coherence, such as [http://en.wikipedia.org/wiki/MSI_protocol MSI], [http://en.wikipedia.org/wiki/MESI_protocol MESI] (aka Illinois), [http://en.wikipedia.org/wiki/MOSI_protocol MOSI], [http://en.wikipedia.org/wiki/MOESI_protocol MOESI], [http://en.wikipedia.org/wiki/MERSI_protocol MERSI], [http://en.wikipedia.org/wiki/MESIF_protocol MESIF], [http://en.wikipedia.org/wiki/Write-once_(cache_coherence) Write-once (cache coherence)], and [[Synapse protocol\|Synapse]], [[Berkeley protocol\|Berkeley]], [[Firefly protocol\|Firefly]] and [[Dragon protocol]]'''.

	=References=		=References=