CSC/ECE 506 Spring 2013/1c ad - Revision history

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	This wiki article explores the Multiple Instruction Single Data architecture(MISD) of parallel architecture as classified by Flynn’s Taxonomy. The article starts with a description of Flynn’s Taxonomy and classification followed by [http://en.wikipedia.org/wiki/MISD MISD architecture] and its realization. It also talks about the authors' and researchers' works on MISD and ends by providing implementations and examples of the architecture.		This wiki article explores the Multiple Instruction Single Data architecture(MISD) of parallel architecture as classified by Flynn’s Taxonomy. The article starts with a description of Flynn’s Taxonomy and classification followed by [http://en.wikipedia.org/wiki/MISD MISD architecture] and its realization. It also talks about the authors' and researchers' works on MISD and ends by providing implementations and examples of the architecture.

	[Note: This topic relates to copy and update of previous ~~wiki's <ref>~~http://wiki.expertiza.ncsu.edu/index.php/CSC/ECE_506_Spring_2012/1c_dm~~</ref>~~ ]		[Note: This topic relates to copy and update of previous [http://wiki.expertiza.ncsu.edu/index.php/CSC/ECE_506_Spring_2012/1c_dm wiki ]

	==Parallel Architecture<ref>http://en.wikipedia.org/wiki/Parallel_computing</ref>==		==Parallel Architecture<ref>http://en.wikipedia.org/wiki/Parallel_computing</ref>==

Adave: /* Glossary */

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Glossary

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	=='''Glossary'''==		=='''Glossary'''==
	*'''CMU''': Carnegie Mellon University

	*'''CU''': Control Unit		*'''CU''': Control Unit
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	*'''FPGA''': Field Programmable Gate Array		*'''FPGA''': Field Programmable Gate Array

	*'''Heterogeneous Systems''': A multiprocessor system with different kind of processors

	*'''Homogeneous System''': A multiprocessor system with same kind of processors

	*'''ILP''': Instruction Level Parallelism		*'''ILP''': Instruction Level Parallelism
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	*'''PFC''': Primary Flight Computer		*'''PFC''': Primary Flight Computer

	*'''SAPO''': Short for Samočinný počítač

	*'''SIMD''': Single Instruction Multiple Data		*'''SIMD''': Single Instruction Multiple Data

Adave: /* ==Systems,Circuits and Deviceshttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5681487&contentType */

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==Systems,Circuits and Deviceshttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5681487&contentType

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	</ref>===		</ref>===

	"An embedded biologically-inspired machine vision processor		"An embedded biologically-inspired machine [http://www.visiononline.org/market-data.cfm?id=73 vision processor]
	that attempts to capture aspects of the computational		that attempts to capture aspects of the computational
	architecture of the brain.Meanwhile,		architecture of the brain.Meanwhile,

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	with the advent of high-speed networking technologies such as fiber optics.Now, the speed at which a processor can execute a communication protocol is the most significant limiting factor in protocol performance. The question is, how can a multimedia application take best advantage of these high-speed networks? By adopting an optimized implementation approach that allows efficient use of the bandwidth available on today's high-speed networks. This means processing data as soon as it arrives from the network. This model increases the processing speed by using a multiple-instruction, single-data (MISD) scheme."		with the advent of high-speed networking technologies such as fiber optics.Now, the speed at which a processor can execute a communication protocol is the most significant limiting factor in protocol performance. The question is, how can a multimedia application take best advantage of these high-speed networks? By adopting an optimized implementation approach that allows efficient use of the bandwidth available on today's high-speed networks. This means processing data as soon as it arrives from the network. This model increases the processing speed by using a multiple-instruction, single-data (MISD) scheme."

	The technique applied a MISD scheme to the OSI protocol		The technique applied a MISD scheme to the [http://en.wikipedia.org/wiki/OSI_protocols OSI protocol]
	to improve the performance of the communication		to improve the performance of the communication
	subsystem.		subsystem.

Adave: /* Acoustics, Speech and Signal Processinghttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1164924&contentType=Journals+%26+Magazines&queryText%3DA+multimicroprocessor+architecture+for+real-time+computation+of+a+class+of+DFT+algorithms

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/* Acoustics, Speech and Signal Processinghttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1164924&contentType=Journals+%26+Magazines&queryText%3DA+multimicroprocessor+architecture+for+real-time+computation+of+a+class+of+DFT+algorithms

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	===Acoustics, Speech and Signal Processing<ref>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1164924&contentType=Journals+%26+Magazines&queryText%3DA+multimicroprocessor+architecture+for+real-time+computation+of+a+class+of+DFT+algorithms</ref>===		===Acoustics, Speech and Signal Processing<ref>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1164924&contentType=Journals+%26+Magazines&queryText%3DA+multimicroprocessor+architecture+for+real-time+computation+of+a+class+of+DFT+algorithms</ref>===

	"Design of a multi microprocessor architecture for real-time computation of a class of DFT algorithms		"Design of a multi microprocessor architecture for real-time computation of a class of [http://en.wikipedia.org/wiki/Discrete_Fourier_transform DFT ]algorithms
	The applications considered require the computation of a subset of an N-input		The applications considered require the computation of a subset of an N-input
	Fourier transform under the assumption of a serial data input.The		Fourier transform under the assumption of a serial data input.The

Adave: /* Fault Tolerant Systemshttp://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance */

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Fault Tolerant Systemshttp://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance

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	===Fault Tolerant Systems<ref>http://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance</ref>===		===Fault Tolerant Systems<ref>http://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance</ref>===

	Fault tolerant systems are designed to handle the possible failures in software, hardware or interfaces.Hardware faults include hard disk failures, input or output device failures, etc.Software and interface faults include driver failures; operator errors, installing unexpected software etc.Hardware faults can be detected and identified by implementing redundant hardware and multiple backups.Software faults can be tolerable by removing the program errors by executing the software redundantly or by implementing small programs that take over the tasks that crash or generate errors.		[http://en.wikipedia.org/wiki/Fault-tolerant_system Fault tolerant systems ]are designed to handle the possible failures in software, hardware or interfaces.Hardware faults include hard disk failures, input or output device failures, etc.Software and interface faults include driver failures; operator errors, installing unexpected software etc.Hardware faults can be detected and identified by implementing redundant hardware and multiple backups.Software faults can be tolerable by removing the program errors by executing the software redundantly or by implementing small programs that take over the tasks that crash or generate errors.

	===MISD image processing systems<ref>Pattern Recognition and Image Analysis, v 6, n 2, p 414-15, April-June 1996</ref>===		===MISD image processing systems<ref>Pattern Recognition and Image Analysis, v 6, n 2, p 414-15, April-June 1996</ref>===

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Implementations of MISD architecture

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Fault Tolerant Systemshttp://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance

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	===Fault Tolerant Systems<ref>http://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance</ref>===		===Fault Tolerant Systems<ref>http://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance</ref>===

	~~The fault~~ tolerant systems are designed to handle the possible failures in software, hardware or interfaces. ~~The hardware~~ faults include hard disk failures, input or output device failures, etc. ~~and the software~~ and interface faults include driver failures; operator errors, installing unexpected software etc. ~~The hardware~~ faults can be detected and identified by implementing redundant hardware and multiple backups. ~~The software~~ faults can be tolerable by removing the program errors by executing the software redundantly or by implementing small programs that take over the tasks that crash or generate errors.		Fault tolerant systems are designed to handle the possible failures in software, hardware or interfaces.Hardware faults include hard disk failures, input or output device failures, etc.Software and interface faults include driver failures; operator errors, installing unexpected software etc.Hardware faults can be detected and identified by implementing redundant hardware and multiple backups.Software faults can be tolerable by removing the program errors by executing the software redundantly or by implementing small programs that take over the tasks that crash or generate errors.

	===MISD image processing systems<ref>Pattern Recognition and Image Analysis, v 6, n 2, p 414-15, April-June 1996</ref>===		===MISD image processing systems<ref>Pattern Recognition and Image Analysis, v 6, n 2, p 414-15, April-June 1996</ref>===

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	===Information Technology Computing<ref>		===Information Technology Computing<ref>
	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=844198&contentType=Conference+Publications&queryText%3DEmbedded+zero+wavelet+coefficient+coding+method+for+FPGA+implementation+of+video+codec+in+real-time+systems</ref>===		http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=844198&contentType=Conference+Publications&queryText%3DEmbedded+zero+wavelet+coefficient+coding+method+for+FPGA+implementation+of+video+codec+in+real-time+systems</ref>===
	[http://ws2.binghamton.edu/fowler/fowler%20personal%20page/EE523_files/Ch_15_4%20EZW%20(PPT)%20revised.pdf Embedded zero wavelet ]coefficient coding method for FPGA implementation of video codec in real-time systems		[http://ws2.binghamton.edu/fowler/fowler%20personal%20page/EE523_files/Ch_15_4%20EZW%20(PPT)%20revised.pdf Embedded zero wavelet]coefficient coding method for FPGA implementation of video codec in real-time systems.

	"The MISD		"The MISD

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	===Information Technology Computing<ref>		===Information Technology Computing<ref>
	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=844198&contentType=Conference+Publications&queryText%3DEmbedded+zero+wavelet+coefficient+coding+method+for+FPGA+implementation+of+video+codec+in+real-time+systems</ref>===		http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=844198&contentType=Conference+Publications&queryText%3DEmbedded+zero+wavelet+coefficient+coding+method+for+FPGA+implementation+of+video+codec+in+real-time+systems</ref>===
	Embedded zero wavelet coefficient coding method for FPGA implementation of video codec in real-time systems		[http://ws2.binghamton.edu/fowler/fowler%20personal%20page/EE523_files/Ch_15_4%20EZW%20(PPT)%20revised.pdf Embedded zero wavelet ]coefficient coding method for FPGA implementation of video codec in real-time systems

	"The MISD		"The MISD
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	enlarged by the fact that fast computing units that has been		enlarged by the fact that fast computing units that has been
	designed that can be re-programmed."		designed that can be re-programmed."

	===Fault Tolerant Systems<ref>http://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance</ref>===		===Fault Tolerant Systems<ref>http://en.wikipedia.org/wiki/Fault-tolerant_computer_system#Types_of_fault_tolerance</ref>===

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	==Implementations of MISD architecture==		==Implementations of MISD architecture==
	Currrently the applications for MISD are limited and commercial implementation scarce due to cost factors.However,it is a research interest in many fields.Describe below are areas where MISD architecture has been implemented		Currrently the applications for MISD are limited and commercial implementation scarce due to cost factors.However,it is a research interest in many fields.Describe below are areas where MISD architecture has been implemented.

	===VLSI : A recursive MISD architecture for pattern matching<ref>http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1308207&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F92%2F29030%2F01308207.pdf%3Farnumber%3D1308207</ref>===		===VLSI : A recursive MISD architecture for pattern matching<ref>http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1308207&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F92%2F29030%2F01308207.pdf%3Farnumber%3D1308207</ref>===
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	"An embedded biologically-inspired machine vision processor		"An embedded biologically-inspired machine vision processor
	that ~~attempt~~ to capture aspects of the computational		that attempts to capture aspects of the computational
	architecture of the brain.Meanwhile,		architecture of the brain.Meanwhile,
	the increasing ubiquity of inexpensive cameras in a wide array		the increasing ubiquity of inexpensive cameras in a wide array
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	architecture is proposed as a solution of the		architecture is proposed as a solution of the
	video coding problem. The architecture is characterised by high speed		video coding problem. The architecture is characterised by high speed
	execution,simplicity and performance		execution,simplicity and performance .
	The important advantages of MISD architectures in real time video systems is		The important advantages of MISD architectures in real time video systems is
	enlarged by the fact that fast computing units that has been		enlarged by the fact that fast computing units that has been
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	=== Supercomputing machine based on MISD architecture<ref>ICS 88. Third International Conference on Supercomputing. Proceedings, Supercomputing '88, p 377-82 vol.3, 1988</ref>===		=== Supercomputing machine based on MISD architecture<ref>ICS 88. Third International Conference on Supercomputing. Proceedings, Supercomputing '88, p 377-82 vol.3, 1988</ref>===

	"Today's successful supercomputers have mostly been developed in the restricted area of numerical computations. Conventional pipelining is adopted to realize high-speed vector processing. From the point of evolution of applications requiring more computational power, however, coming supercomputers should be used even for symbolic computations.The pipelined supercomputing of function-level programs dealing with list-structured data can be performed on the general-purpose pipeline designed to be an MISD architecture. Effectiveness of the approach is demonstrated by the simulation results of benchmark programs"		"Today's successful supercomputers have mostly been developed in the restricted area of numerical computations. Conventional pipelining is adopted to realize high-speed [http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf vector processing]. From the point of evolution of applications requiring more computational power, however, coming supercomputers should be used even for symbolic computations.The pipelined supercomputing of function-level programs dealing with list-structured data can be performed on the general-purpose pipeline designed to be an MISD architecture. Effectiveness of the approach is demonstrated by the simulation results of benchmark programs."

	====The Flight Control System – MISD Example for fault tolerance====		====The Flight Control System – MISD Example for fault tolerance====