CSC/ECE 506 Spring 2013/10b ps - Revision history

Ppraman2 at 23:25, 10 April 2013

2013-04-10T23:25:49Z

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	[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 11. http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf] <br />		[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 11. http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf] <br />
	[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf 12. http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf] <br />		[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf 12. http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf] <br />
	[http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt 23. http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt]		[http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt 13. http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt]

Ppraman2 at 23:25, 10 April 2013

2013-04-10T23:25:18Z

Show changes

Ppraman2 at 23:18, 10 April 2013

2013-04-10T23:18:31Z

← Older revision		Revision as of 23:18, 10 April 2013
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	[http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html 1. http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html] <br />		[http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html 1. http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html] <br />
	[http://pic.dhe.ibm.com/infocenter/lnxinfo/v3r0m0/topic/liaaw/ordering.2006.03.13a.pdf 2. http://pic.dhe.ibm.com/infocenter/lnxinfo/v3r0m0/topic/liaaw/ordering.2006.03.13a.pdf] <br />		[http://pic.dhe.ibm.com/infocenter/lnxinfo/v3r0m0/topic/liaaw/ordering.2006.03.13a.pdf 2. http://pic.dhe.ibm.com/infocenter/lnxinfo/v3r0m0/topic/liaaw/ordering.2006.03.13a.pdf] <br />
	~~[http://dl.acm.org/citation.cfm?id=1941553.1941594 3. http://dl.acm.org/citation.cfm?id=1941553.1941594] <br />~~
	[http://home.deib.polimi.it/speziale/tech/memory_consistency/mc.html 4. http://home.deib.polimi.it/speziale/tech/memory_consistency/mc.html] <br />		[http://home.deib.polimi.it/speziale/tech/memory_consistency/mc.html 4. http://home.deib.polimi.it/speziale/tech/memory_consistency/mc.html] <br />
	~~[http://homes.cs.washington.edu/~djg/papers/asf_micro2010.pdf 5. http://homes.cs.washington.edu/~djg/papers/asf_micro2010.pdf] <br />~~
	[http://people.ee.duke.edu/~sorin/papers/asplos10_consistency.pdf 6. http://people.ee.duke.edu/~sorin/papers/asplos10_consistency.pdf] <br />		[http://people.ee.duke.edu/~sorin/papers/asplos10_consistency.pdf 6. http://people.ee.duke.edu/~sorin/papers/asplos10_consistency.pdf] <br />
	[http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.06.07c.pdf 7. http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.06.07c.pdf] <br />		[http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.06.07c.pdf 7. http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.06.07c.pdf] <br />
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	[http://www.montefiore.ulg.ac.be/~pw/cours/psfiles/struct-cours12-e.pdf 9. http://www.montefiore.ulg.ac.be/~pw/cours/psfiles/struct-cours12-e.pdf] <br />		[http://www.montefiore.ulg.ac.be/~pw/cours/psfiles/struct-cours12-e.pdf 9. http://www.montefiore.ulg.ac.be/~pw/cours/psfiles/struct-cours12-e.pdf] <br />
	[http://www2.engr.arizona.edu/~ece569a/Readings/ppt/memory.ppt 10. http://www2.engr.arizona.edu/~ece569a/Readings/ppt/memory.ppt] <br />		[http://www2.engr.arizona.edu/~ece569a/Readings/ppt/memory.ppt 10. http://www2.engr.arizona.edu/~ece569a/Readings/ppt/memory.ppt] <br />
	~~[http://ipdps.cc.gatech.edu/2000/fmppta/18000989.pdf 11. http://ipdps.cc.gatech.edu/2000/fmppta/18000989.pdf] <br />~~
	~~[http://preshing.com/20120930/weak-vs-strong-memory-models 12. http://preshing.com/20120930/weak-vs-strong-memory-models] <br />~~
	~~[http://csg.csail.mit.edu/pubs/memos/Memo-493/memo-493.pdf 13. http://csg.csail.mit.edu/pubs/memos/Memo-493/memo-493.pdf] <br />~~
	~~[http://classes.soe.ucsc.edu/cmpe221/Spring05/papers/29multi.pdf 14. http://classes.soe.ucsc.edu/cmpe221/Spring05/papers/29multi.pdf] <br />~~
	[http://os.inf.tu-dresden.de/Studium/DOS/SS2009/04-Coherency.pdf 15. http://os.inf.tu-dresden.de/Studium/DOS/SS2009/04-Coherency.pdf] <br />		[http://os.inf.tu-dresden.de/Studium/DOS/SS2009/04-Coherency.pdf 15. http://os.inf.tu-dresden.de/Studium/DOS/SS2009/04-Coherency.pdf] <br />
	[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16. http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf] <br />		[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16. http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf] <br />
	[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17. http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf] <br />		[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17. http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf] <br />
	[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf 18. http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf] <br />		[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf 18. http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/pldi105-sarkar.pdf] <br />
	~~[http://www.cs.utah.edu/formal_verification/publications/conferences/pdf/charme03.pdf 19. http://www.cs.utah.edu/formal_verification/publications/conferences/pdf/charme03.pdf] <br />~~
	~~[http://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.tphols.pdf 20. http://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.tphols.pdf]~~
	[http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt 21. http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt]		[http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt 21. http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt]

Ppraman2 at 23:12, 10 April 2013

2013-04-10T23:12:39Z

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	[http://www.cs.utah.edu/formal_verification/publications/conferences/pdf/charme03.pdf 19. http://www.cs.utah.edu/formal_verification/publications/conferences/pdf/charme03.pdf] <br />		[http://www.cs.utah.edu/formal_verification/publications/conferences/pdf/charme03.pdf 19. http://www.cs.utah.edu/formal_verification/publications/conferences/pdf/charme03.pdf] <br />
	[http://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.tphols.pdf 20. http://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.tphols.pdf]		[http://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.tphols.pdf 20. http://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.tphols.pdf]
	[http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt]		[http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt 21. http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt]

Skey: /* Mobile Devices */

2013-04-10T21:29:37Z

Mobile Devices

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	2. The memory system does not guarantee that writes will become visible to all other hardware threads at the same point. <br />		2. The memory system does not guarantee that writes will become visible to all other hardware threads at the same point. <br />
	<br />		<br />
	In order to conceptualize the architecture think of each as effectively having it’s own copy of memory. A write by one thread may propagate to other threads in any order. When this propagation happens they may be interleaved arbitrarily. This allows for great hardware execution optimization but also put a responsibility on the programmers shoulders to instill barriers if they want to constrain this behavior. [http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]		In order to conceptualize the architecture think of each as effectively having it’s own copy of memory. A write by one thread may propagate to other threads in any order. When this propagation happens they may be interleaved arbitrarily. This allows for great hardware execution optimization but also put a responsibility on the programmers shoulders to instill barriers if they want to constrain this behavior. [[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]]

	[[File:ARM_Star.png‎\|center\|frame\|\|Conceptual ARM architecture]]		[[File:ARM_Star.png‎\|center\|frame\|\|Conceptual ARM architecture]]

	Given these properties, a greater focus is put on the programmer-observable behavior. This is the behavior exhibited by a multithreaded program as it is executed and analyzing the results. This is not related to performance but instead the correctness of the results. The looseness of the ARM architecture must be taken into account by the programmer and they must realize that their multithreaded application may exhibit different observable behavior given the conditions it is run under. [http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17] <br />		Given these properties, a greater focus is put on the programmer-observable behavior. This is the behavior exhibited by a multithreaded program as it is executed and analyzing the results. This is not related to performance but instead the correctness of the results. The looseness of the ARM architecture must be taken into account by the programmer and they must realize that their multithreaded application may exhibit different observable behavior given the conditions it is run under. [[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]] <br />

	[[File:ARM_tree.png‎\|center\|frame\|\|ARM Thread level execution]]		[[File:ARM_tree.png‎\|center\|frame\|\|ARM Thread level execution]]

Skey at 21:28, 10 April 2013

2013-04-10T21:28:48Z

← Older revision		Revision as of 21:28, 10 April 2013
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	2. The memory system does not guarantee that writes will become visible to all other hardware threads at the same point. <br />		2. The memory system does not guarantee that writes will become visible to all other hardware threads at the same point. <br />
	<br />		<br />
	In order to conceptualize the architecture think of each as effectively having it’s own copy of memory. A write by one thread may propagate to other threads in any order. When this propagation happens they may be interleaved arbitrarily. This allows for great hardware execution optimization but also put a responsibility on the programmers shoulders to instill barriers if they want to constrain this behavior.		In order to conceptualize the architecture think of each as effectively having it’s own copy of memory. A write by one thread may propagate to other threads in any order. When this propagation happens they may be interleaved arbitrarily. This allows for great hardware execution optimization but also put a responsibility on the programmers shoulders to instill barriers if they want to constrain this behavior. [http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]

	[[File:ARM_Star.png‎\|center\|frame\|\|Conceptual ARM architecture]]		[[File:ARM_Star.png‎\|center\|frame\|\|Conceptual ARM architecture]]

	Given these properties, a greater focus is put on the programmer-observable behavior. This is the behavior exhibited by a multithreaded program as it is executed and analyzing the results. This is not related to performance but instead the correctness of the results. The looseness of the ARM architecture must be taken into account by the programmer and they must realize that their multithreaded application may exhibit different observable behavior given the conditions it is run under.<br />		Given these properties, a greater focus is put on the programmer-observable behavior. This is the behavior exhibited by a multithreaded program as it is executed and analyzing the results. This is not related to performance but instead the correctness of the results. The looseness of the ARM architecture must be taken into account by the programmer and they must realize that their multithreaded application may exhibit different observable behavior given the conditions it is run under. [http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17] <br />

	[[File:ARM_tree.png‎\|center\|frame\|\|ARM Thread level execution]]		[[File:ARM_tree.png‎\|center\|frame\|\|ARM Thread level execution]]

Ppraman2 at 02:37, 10 April 2013

2013-04-10T02:37:32Z

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	The IBM PowerPC model exposes multiple-copy semantics of memory to the programmer as shown in the conceptual system above. The safety net fence instruction is called SYNC which is similar to the MB fence instruction of the Alpha systems. However, SYNC between two reads allows the instructions to occur out of program order. Also the PowerPC allows a write to be seen early by another processor’s read. Hence a read-modify-write operation may be needed to enforce program order between two reads to the same location as well as to make writes appear atomic. [[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]		The IBM PowerPC model exposes multiple-copy semantics of memory to the programmer as shown in the conceptual system above. The safety net fence instruction is called SYNC which is similar to the MB fence instruction of the Alpha systems. However, SYNC between two reads allows the instructions to occur out of program order. Also the PowerPC allows a write to be seen early by another processor’s read. Hence a read-modify-write operation may be needed to enforce program order between two reads to the same location as well as to make writes appear atomic. [[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]

	The table below summarizes the program constraint under each model we have described so far and other commercial servers that also implement these three Relaxed Consistency models (these additional examples are not discussed above)[[http://pic.dhe.ibm.com/infocenter/lnxinfo/v3r0m0/topic/liaaw/ordering.2006.03.13a.pdf 2], [http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16], [http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]]..		The table below summarizes the program constraint under each model we have described so far and other commercial servers that also implement these three Relaxed Consistency models (these additional examples are not discussed above)[[http://pic.dhe.ibm.com/infocenter/lnxinfo/v3r0m0/topic/liaaw/ordering.2006.03.13a.pdf 2], [http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16], [http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]].

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Ppraman2 at 02:36, 10 April 2013

2013-04-10T02:36:23Z

← Older revision		Revision as of 02:36, 10 April 2013
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	The IBM PowerPC model exposes multiple-copy semantics of memory to the programmer as shown in the conceptual system above. The safety net fence instruction is called SYNC which is similar to the MB fence instruction of the Alpha systems. However, SYNC between two reads allows the instructions to occur out of program order. Also the PowerPC allows a write to be seen early by another processor’s read. Hence a read-modify-write operation may be needed to enforce program order between two reads to the same location as well as to make writes appear atomic. [[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]		The IBM PowerPC model exposes multiple-copy semantics of memory to the programmer as shown in the conceptual system above. The safety net fence instruction is called SYNC which is similar to the MB fence instruction of the Alpha systems. However, SYNC between two reads allows the instructions to occur out of program order. Also the PowerPC allows a write to be seen early by another processor’s read. Hence a read-modify-write operation may be needed to enforce program order between two reads to the same location as well as to make writes appear atomic. [[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]

	The table below summarizes the program constraint under each model we have described so far and other commercial servers that also implement these three Relaxed Consistency models (these additional examples are not discussed above).		The table below summarizes the program constraint under each model we have described so far and other commercial servers that also implement these three Relaxed Consistency models (these additional examples are not discussed above)[[http://pic.dhe.ibm.com/infocenter/lnxinfo/v3r0m0/topic/liaaw/ordering.2006.03.13a.pdf 2], [http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16], [http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]]..

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Ppraman2 at 02:30, 10 April 2013

2013-04-10T02:30:18Z

Skey: /* How Memory Consistency Used to be Done */

2013-04-10T02:26:54Z

How Memory Consistency Used to be Done

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	The advantages to a model like this is that it is easy to understand from a programmer perspective. Unfortunately the rules put in place by this model are very restrictive and can negatively impact performance. Sequential Consistency disallows the reordering of shared memory operations between processors. The drawbacks of this strict model produces high latency and very little benefit of true serial execution. This is because reads tend to be closely interleaved with writes yielding very little utilization of the write buffer.[[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]]		The advantages to a model like this is that it is easy to understand from a programmer perspective. Unfortunately the rules put in place by this model are very restrictive and can negatively impact performance. Sequential Consistency disallows the reordering of shared memory operations between processors. The drawbacks of this strict model produces high latency and very little benefit of true serial execution. This is because reads tend to be closely interleaved with writes yielding very little utilization of the write buffer.[[http://www.cl.cam.ac.uk/~pes20/ppc-supplemental/test7.pdf 17]]

			[[File:SeqC.jpg\|center\|frame\|\|Conceptual Model for Sequential Consistency Model]]

	=Memory Consistency Today=		=Memory Consistency Today=

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	For Write to Write relaxation we allow:		For Write to Write relaxation we allow[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]:
	1. Two writes to execute out of program order.		1. Two writes to execute out of program order.

	2. A write followed by a read execute out of program order.		2. A write followed by a read execute out of program order.

	This relaxation enables a number of hardware optimizations, including write merging in a write buffer and overlapping multiple write misses, thus servicing the writes at a much faster rate. However, this relaxation is still not sufficiently flexible to be useful to a compiler. The SPARC V8 Partial Store Ordering model (PSO) is an example of a system that uses Write to Write relaxation.		This relaxation enables a number of hardware optimizations, including write merging in a write buffer and overlapping multiple write misses, thus servicing the writes at a much faster rate. However, this relaxation is still not sufficiently flexible to be useful to a compiler. The SPARC V8 Partial Store Ordering model (PSO) is an example of a system that uses Write to Write relaxation.[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]


	'''''SPARC V8 Partial Store Ordering (PSO)'''''		'''''SPARC V8 Partial Store Ordering (PSO)'''''

	The Partial Store Ordering (PSO) model is similar to the TSO model for SPARC V8. The figure below shows mostly an identical conceptual system, with only a slight difference in the program order. This relaxation allows writes to locations to be overlapped if they are not to same locations. This is represented by the dashed line between the W's in the program order figure. Safety net for the program order is provided through a fence instruction, called the store barrier or STBAR, which may be used to enforce the program order between writes.		The Partial Store Ordering (PSO) model is similar to the TSO model for SPARC V8. The figure below shows mostly an identical conceptual system, with only a slight difference in the program order. This relaxation allows writes to locations to be overlapped if they are not to same locations. This is represented by the dashed line between the W's in the program order figure. Safety net for the program order is provided through a fence instruction, called the store barrier or STBAR, which may be used to enforce the program order between writes.[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]

	[[File:PSO.jpg\|center\|frame\|\|Conceptual Model of SPARC V8 PSO]]		[[File:PSO.jpg\|center\|frame\|\|Conceptual Model of SPARC V8 PSO]]
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	[[File:Code2.jpg\|center\|frame\|\|Conceptual Model of SPARC V8 PSO]]		[[File:Code2.jpg\|center\|frame\|\|Conceptual Model of SPARC V8 PSO]]

	With relaxed Write to Read models, the only value for (u,v) is (1,1). With PSO, since it allows writes to different locations to complete out of program order, it also allows the outcomes (0,0) or (0,1) or (1,0) for (u,v). In this example, STBAR instruction needs to be placed immediately before c1 on P1 in order to disallow all outcomes except (1,1).[9]		With relaxed Write to Read models, the only value for (u,v) is (1,1). With PSO, since it allows writes to different locations to complete out of program order, it also allows the outcomes (0,0) or (0,1) or (1,0) for (u,v). In this example, STBAR instruction needs to be placed immediately before c1 on P1 in order to disallow all outcomes except (1,1).[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]


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	For Read to Read and Read to Write we shed the restrictions on program order between all operations, including read to read and read followed by write to different locations . This flexibility provides the possibility of hiding the latency of read operations by implementing true non-blocking reads in the context of either static (in-order) or dynamic (out-of-order) scheduling processors, supported by techniques such as non-blocking (lockup-free) caches and speculative execution. The compiler also has full flexibility to reorder operations.		For Read to Read and Read to Write we shed the restrictions on program order between all operations, including read to read and read followed by write to different locations . This flexibility provides the possibility of hiding the latency of read operations by implementing true non-blocking reads in the context of either static (in-order) or dynamic (out-of-order) scheduling processors, supported by techniques such as non-blocking (lockup-free) caches and speculative execution. The compiler also has full flexibility to reorder operations.[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]

	The DEC Alpha, Relaxed Memory Order (RMO) on the SPARC V9, and PowerPC are examples of systems using this model. Except for Alpha, all the other models allow reordering of two reads to the same location.		The DEC Alpha, Relaxed Memory Order (RMO) on the SPARC V9, and PowerPC are examples of systems using this model. Except for Alpha, all the other models allow reordering of two reads to the same location.[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]

	All of the models in this group allow a processor to read its own write early with the exception of the PowerPC. All these architectures provide explicit fence instructions to ensure program order, however it should be noted that the frequent use of fence instructions can incur a significant overhead due to an increase in the number of instructions and the extra delay that may be associated with executing fence instructions.		All of the models in this group allow a processor to read its own write early with the exception of the PowerPC. All these architectures provide explicit fence instructions to ensure program order, however it should be noted that the frequent use of fence instructions can incur a significant overhead due to an increase in the number of instructions and the extra delay that may be associated with executing fence instructions.[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]


	'''''DEC Alpha'''''		'''''DEC Alpha'''''

	The DEC Alpha allows reads and writes to different locations to complete out of program order unless there is a fence instruction between them. Memory operations to the same location, including reads, are required to complete in program order. Safety net for program order is provided through the fence instructions, the memory barrier (MB) and the write memory barrier (WMB). The MB instruction can be used to maintain program order between any memory operations, while WMB instruction provides this guarantee only among write operations. The Alpha model does not require a safety net for write atomicity.		The DEC Alpha allows reads and writes to different locations to complete out of program order unless there is a fence instruction between them. Memory operations to the same location, including reads, are required to complete in program order. Safety net for program order is provided through the fence instructions, the memory barrier (MB) and the write memory barrier (WMB). The MB instruction can be used to maintain program order between any memory operations, while WMB instruction provides this guarantee only among write operations. The Alpha model does not require a safety net for write atomicity.[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]

	[[File:Alpha.jpg\|center\|frame\|\|Conceptual Model of SPARC V8 PSO]]		[[File:Alpha.jpg\|center\|frame\|\|Conceptual Model of SPARC V8 PSO]]


	The conceptual system shown above is the same as IBM 370 which requires a read to return the value of the last write operation to the same location. But since we can relax the program order from a write to a read, we can safely exploit optimizations such as read forwarding.		The conceptual system shown above is the same as IBM 370 which requires a read to return the value of the last write operation to the same location. But since we can relax the program order from a write to a read, we can safely exploit optimizations such as read forwarding.[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]


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	The SPARC V9 architecture uses RMO which is an extension of the TSO and PSO models used in SPARC V8. The Read to Read, Read to write program order is relaxed in this model, like in PSO. But a Read to Write or the order between two writes to the same location are not relaxed. This is shown in the figure for program order below.		The SPARC V9 architecture uses RMO which is an extension of the TSO and PSO models used in SPARC V8. The Read to Read, Read to write program order is relaxed in this model, like in PSO. But a Read to Write or the order between two writes to the same location are not relaxed. This is shown in the figure for program order below.
	RMO provides four types of fences [F1 through F4] that allow program order to be selectively maintained between any two types of operations. A single fence instruction, MEMBAR, can specify a combination of the above fence types by setting the appropriate bits in a four-bit opcode. No safety net for write atomicity is required.		RMO provides four types of fences [F1 through F4] that allow program order to be selectively maintained between any two types of operations. A single fence instruction, MEMBAR, can specify a combination of the above fence types by setting the appropriate bits in a four-bit opcode. No safety net for write atomicity is required.[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]


	'''''IBM PowerPC'''''		'''''IBM PowerPC'''''

	The PowerPC does constrain the program order in some situations such as:		The PowerPC does constrain the program order in some situations such as[[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]:

	1. Between sub-operations. That is each operation may consist of multiple sub-operations and that all sub-operations of the first operation must complete before any sub-operations of the second operation, represented by the double lines between operations in the figure below.		1. Between sub-operations. That is each operation may consist of multiple sub-operations and that all sub-operations of the first operation must complete before any sub-operations of the second operation, represented by the double lines between operations in the figure below.
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	3. Among conflicting operations.		3. Among conflicting operations.

	The IBM PowerPC model exposes multiple-copy semantics of memory to the programmer as shown in the conceptual system above. The safety net fence instruction is called SYNC which is similar to the MB fence instruction of the Alpha systems. However, SYNC between two reads allows the instructions to occur out of program order. Also the PowerPC allows a write to be seen early by another processor’s read. Hence a read-modify-write operation may be needed to enforce program order between two reads to the same location as well as to make writes appear atomic.		The IBM PowerPC model exposes multiple-copy semantics of memory to the programmer as shown in the conceptual system above. The safety net fence instruction is called SYNC which is similar to the MB fence instruction of the Alpha systems. However, SYNC between two reads allows the instructions to occur out of program order. Also the PowerPC allows a write to be seen early by another processor’s read. Hence a read-modify-write operation may be needed to enforce program order between two reads to the same location as well as to make writes appear atomic. [[http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf 16]]

	The table below summarizes the program constraint under each model we have described so far and other commercial servers that also implement these three Relaxed Consistency models (these additional examples are not discussed above).		The table below summarizes the program constraint under each model we have described so far and other commercial servers that also implement these three Relaxed Consistency models (these additional examples are not discussed above).