CSC/ECE 506 Spring 2012/preface - Revision history

Pmfernan: /* MSI, MESI, MESIF, And MOESI Protocols on Real Architectures */

2012-05-15T21:30:47Z

MSI, MESI, MESIF, And MOESI Protocols on Real Architectures

← Older revision		Revision as of 21:30, 15 May 2012
Line 91:		Line 91:
	The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.		The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.
	==MSI, MESI, MESIF, And MOESI Protocols on Real Architectures==		==MSI, MESI, MESIF, And MOESI Protocols on Real Architectures==
	Now in Spring 2012, <ref name=A43 /> and <ref name=A44 /> develop a similar topic as <ref name=A42 />, '''MSI, MESI, MESIF, And MOESI Protocols on Real Architectures''', and the wiki pages are very close to those of the previous year. <ref name=A44 /> adds a chapter on MESI and ARM11 and Cortex-A9 MPCore, which are in fashion these days. It also presents a chapter on Instruction Prefetching and another in Word Invalidation. <ref name=D1 /> is a very good with an excellent coverage.		Now in Spring 2012, <ref name=A43 /> and <ref name=A44 /> develop a similar topic as <ref name=A42 />, '''MSI, MESI, MESIF, And MOESI Protocols on Real Architectures''', and the wiki pages are very close to those of the previous year. <ref name=A44 /> adds a chapter on MESI and ARM11 and Cortex-A9 MPCore, which are in fashion these days. It also presents a chapter on Instruction Prefetching and another in Word Invalidation. <ref name=D1 /> is a very good page with an excellent coverage.

	==Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations==		==Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations==

Pmfernan: /* TLB Coherence in Multiprocessing */

2012-05-11T03:11:25Z

TLB Coherence in Multiprocessing

← Older revision		Revision as of 03:11, 11 May 2012
Line 81:		Line 81:
	In the first section of this chapter, <ref name=A37 /> and <ref name=A38 />, from 2011, bring the topic of '''Cache Coherence and Memory Consistency in Share Memory Systems'''. <ref name=A37 /> starts by talking about the advantages and disadvantages of the share memory architectures and the hardware support is needed to achieve them. Then, it describes in depth both the cache coherence and memory consistency problems, passing to talk about the Peterson's Algorithm and Page Tables.		In the first section of this chapter, <ref name=A37 /> and <ref name=A38 />, from 2011, bring the topic of '''Cache Coherence and Memory Consistency in Share Memory Systems'''. <ref name=A37 /> starts by talking about the advantages and disadvantages of the share memory architectures and the hardware support is needed to achieve them. Then, it describes in depth both the cache coherence and memory consistency problems, passing to talk about the Peterson's Algorithm and Page Tables.
	==TLB Coherence in Multiprocessing==		==TLB Coherence in Multiprocessing==
	In the second section '''TLB Coherence in Multiprocessing''', we get into the Spring 2012 pages, <ref name=A39 /> and <ref name=A40 />. <ref name=A39 /> is a very good page and starts giving us a background on the subject, introducing the concepts of virtual memory, paging and defining TLBs. Following it describes the coherence problems that we find when we work in with TLBs in a multiprocessor environment, like swap-outs, protection changes or mapping changes. Next, it discusses approaches to the TLB coherence and its elements and presents some strategies to face the problem, that is, using Virtually Indexes Cache, which would eliminate TLBs altogether; TLB Shootdowns, a mixture of synchronization and messaging, with descriptions of methods and implementations; Hierarchical TLBs, where they are organized in levels, like cache; Instruction-based Validation; an approach based on an Address Space Identifier (ASID) and a Validation Based solution, where invalidations are postponed until memory is accessed. Finally, as an example, the page describes the Unified Cache and TLB coherence solution, the Unified Instruction/Translation/Data (UNITD) Coherence protocol by Romanescu et al; giving some background of the reasons that took to its development, and then thoroughly discussing its implementation and performance. <ref name=E1 > is also a complete and excellent page, with sections related to multiprocessors and Poison Bit Technique.		In the second section '''TLB Coherence in Multiprocessing''', we get into the Spring 2012 pages, <ref name=A39 /> and <ref name=A40 />. <ref name=A39 /> is a very good page and starts giving us a background on the subject, introducing the concepts of virtual memory, paging and defining TLBs. Following it describes the coherence problems that we find when we work in with TLBs in a multiprocessor environment, like swap-outs, protection changes or mapping changes. Next, it discusses approaches to the TLB coherence and its elements and presents some strategies to face the problem, that is, using Virtually Indexes Cache, which would eliminate TLBs altogether; TLB Shootdowns, a mixture of synchronization and messaging, with descriptions of methods and implementations; Hierarchical TLBs, where they are organized in levels, like cache; Instruction-based Validation; an approach based on an Address Space Identifier (ASID) and a Validation Based solution, where invalidations are postponed until memory is accessed. Finally, as an example, the page describes the Unified Cache and TLB coherence solution, the Unified Instruction/Translation/Data (UNITD) Coherence protocol by Romanescu et al; giving some background of the reasons that took to its development, and then thoroughly discussing its implementation and performance. <ref name=E1 /> is also a complete and excellent page, with sections related to multiprocessors and Poison Bit Technique.

	=Chapter 8: Bus-Based Coherent Multiprocessors=		=Chapter 8: Bus-Based Coherent Multiprocessors=

Pmfernan: /* TLB Coherence in Multiprocessing */

2012-05-11T03:11:07Z

TLB Coherence in Multiprocessing

← Older revision		Revision as of 03:11, 11 May 2012
Line 87:		Line 87:

	This dense chapter of the Solihin<ref name=A1 /> talks about bus-based architecture and how to assure coherence in a multiprocessor system that uses it. It defines the bus, its characteristics and transactions and the design choices that we can have. Then it goes into bus arbitration and snooping-based coherence and describes the protocols that use it, like MSI, MESI, MOESI, Dragon or Firefly. While the first set of wikis connect those protocols with the real machine implementations they were develop for, the lasts go deeper into implementation issues and, being an topic of great relevance lately, power schemes.		This dense chapter of the Solihin<ref name=A1 /> talks about bus-based architecture and how to assure coherence in a multiprocessor system that uses it. It defines the bus, its characteristics and transactions and the design choices that we can have. Then it goes into bus arbitration and snooping-based coherence and describes the protocols that use it, like MSI, MESI, MOESI, Dragon or Firefly. While the first set of wikis connect those protocols with the real machine implementations they were develop for, the lasts go deeper into implementation issues and, being an topic of great relevance lately, power schemes.

	==Introduction To Bus-Based Cache Coherence In Real Machines==		==Introduction To Bus-Based Cache Coherence In Real Machines==
	The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.		The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.

Pmfernan: /* Chapter 7:Introduction to Shared Memory Multiprocessors */

2012-05-11T03:10:38Z

Chapter 7:Introduction to Shared Memory Multiprocessors

← Older revision		Revision as of 03:10, 11 May 2012
Line 74:		Line 74:

	=Chapter 7:Introduction to Shared Memory Multiprocessors=		=Chapter 7:Introduction to Shared Memory Multiprocessors=
	Pages in this chapter: <ref name=A37>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch7_jp Spring_2011/ch7_jp]</ref><ref name=A38>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch7_ss Spring_2011/ch7_ss]</ref><ref name=A39>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/7b_pk Spring_2012/7b_pk]</ref><ref name=A40>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/7b_yw Spring_2012/7b_yw]</ref>		Pages in this chapter: <ref name=A37>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch7_jp Spring_2011/ch7_jp]</ref><ref name=A38>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch7_ss Spring_2011/ch7_ss]</ref><ref name=A39>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/7b_pk Spring_2012/7b_pk]</ref><ref name=A40>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/7b_yw Spring_2012/7b_yw]</ref><ref name=E1>[http://expertiza.csc.ncsu.edu/wiki/index.php/ECE506_CSC/ECE_506_Spring_2012/7b_na_2012/7b_na]</ref>

	Chapter 7 of the Solihin <ref name=A1 /> text treats the topic of cache coherence. It discuses the necessity of having hardware support in shared memory systems to ensure ordering and describes it. It also browses through the concepts of cache coherence in systems with caches, memory consistency models and synchronization support. The first wiki pages in this section complement the chapter up to some state, following the structure of the book. The second set introduces the concept of TLB coherence, which is not treated deeply in the text.		Chapter 7 of the Solihin <ref name=A1 /> text treats the topic of cache coherence. It discuses the necessity of having hardware support in shared memory systems to ensure ordering and describes it. It also browses through the concepts of cache coherence in systems with caches, memory consistency models and synchronization support. The first wiki pages in this section complement the chapter up to some state, following the structure of the book. The second set introduces the concept of TLB coherence, which is not treated deeply in the text.
Line 81:		Line 81:
	In the first section of this chapter, <ref name=A37 /> and <ref name=A38 />, from 2011, bring the topic of '''Cache Coherence and Memory Consistency in Share Memory Systems'''. <ref name=A37 /> starts by talking about the advantages and disadvantages of the share memory architectures and the hardware support is needed to achieve them. Then, it describes in depth both the cache coherence and memory consistency problems, passing to talk about the Peterson's Algorithm and Page Tables.		In the first section of this chapter, <ref name=A37 /> and <ref name=A38 />, from 2011, bring the topic of '''Cache Coherence and Memory Consistency in Share Memory Systems'''. <ref name=A37 /> starts by talking about the advantages and disadvantages of the share memory architectures and the hardware support is needed to achieve them. Then, it describes in depth both the cache coherence and memory consistency problems, passing to talk about the Peterson's Algorithm and Page Tables.
	==TLB Coherence in Multiprocessing==		==TLB Coherence in Multiprocessing==
	In the second section '''TLB Coherence in Multiprocessing''', we get into the Spring 2012 pages, <ref name=A39 /> and <ref name=A40 />. <ref name=A39 /> is a very good page and starts giving us a background on the subject, introducing the concepts of virtual memory, paging and defining TLBs. Following it describes the coherence problems that we find when we work in with TLBs in a multiprocessor environment, like swap-outs, protection changes or mapping changes. Next, it discusses approaches to the TLB coherence and its elements and presents some strategies to face the problem, that is, using Virtually Indexes Cache, which would eliminate TLBs altogether; TLB Shootdowns, a mixture of synchronization and messaging, with descriptions of methods and implementations; Hierarchical TLBs, where they are organized in levels, like cache; Instruction-based Validation; an approach based on an Address Space Identifier (ASID) and a Validation Based solution, where invalidations are postponed until memory is accessed. Finally, as an example, the page describes the Unified Cache and TLB coherence solution, the Unified Instruction/Translation/Data (UNITD) Coherence protocol by Romanescu et al; giving some background of the reasons that took to its development, and then thoroughly discussing its implementation and performance.		In the second section '''TLB Coherence in Multiprocessing''', we get into the Spring 2012 pages, <ref name=A39 /> and <ref name=A40 />. <ref name=A39 /> is a very good page and starts giving us a background on the subject, introducing the concepts of virtual memory, paging and defining TLBs. Following it describes the coherence problems that we find when we work in with TLBs in a multiprocessor environment, like swap-outs, protection changes or mapping changes. Next, it discusses approaches to the TLB coherence and its elements and presents some strategies to face the problem, that is, using Virtually Indexes Cache, which would eliminate TLBs altogether; TLB Shootdowns, a mixture of synchronization and messaging, with descriptions of methods and implementations; Hierarchical TLBs, where they are organized in levels, like cache; Instruction-based Validation; an approach based on an Address Space Identifier (ASID) and a Validation Based solution, where invalidations are postponed until memory is accessed. Finally, as an example, the page describes the Unified Cache and TLB coherence solution, the Unified Instruction/Translation/Data (UNITD) Coherence protocol by Romanescu et al; giving some background of the reasons that took to its development, and then thoroughly discussing its implementation and performance. <ref name=E1 > is also a complete and excellent page, with sections related to multiprocessors and Poison Bit Technique.

	=Chapter 8: Bus-Based Coherent Multiprocessors=		=Chapter 8: Bus-Based Coherent Multiprocessors=

Pmfernan: /* MSI, MESI, MESIF, And MOESI Protocols on Real Architectures */

2012-05-10T21:21:34Z

MSI, MESI, MESIF, And MOESI Protocols on Real Architectures

← Older revision		Revision as of 21:21, 10 May 2012
Line 90:		Line 90:
	The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.		The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.
	==MSI, MESI, MESIF, And MOESI Protocols on Real Architectures==		==MSI, MESI, MESIF, And MOESI Protocols on Real Architectures==
	Now in Spring 2012, <ref name=A43 /> and <ref name=A44 /> develop a similar topic as <ref name=A42 />, '''MSI, MESI, MESIF, And MOESI Protocols on Real Architectures''', and the wiki pages are very close to those of the previous year. <ref name=A44 /> adds a chapter on MESI and ARM11 and Cortex-A9 MPCore, which are in fashion these days. It also presents a chapter on Instruction Prefetching and another in Word Invalidation. <ref name=D1 /> is a very good ~~page and article~~ with an excellent coverage.		Now in Spring 2012, <ref name=A43 /> and <ref name=A44 /> develop a similar topic as <ref name=A42 />, '''MSI, MESI, MESIF, And MOESI Protocols on Real Architectures''', and the wiki pages are very close to those of the previous year. <ref name=A44 /> adds a chapter on MESI and ARM11 and Cortex-A9 MPCore, which are in fashion these days. It also presents a chapter on Instruction Prefetching and another in Word Invalidation. <ref name=D1 /> is a very good with an excellent coverage.

	==Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations==		==Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations==

Pmfernan: /* MSI, MESI, MESIF, And MOESI Protocols on Real Architectures */

2012-05-10T21:08:28Z

MSI, MESI, MESIF, And MOESI Protocols on Real Architectures

← Older revision		Revision as of 21:08, 10 May 2012
Line 90:		Line 90:
	The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.		The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.
	==MSI, MESI, MESIF, And MOESI Protocols on Real Architectures==		==MSI, MESI, MESIF, And MOESI Protocols on Real Architectures==
	Now in Spring 2012, <ref name=A43 /> and <ref name=A44 /> develop a similar topic as <ref name=A42 />, '''MSI, MESI, MESIF, And MOESI Protocols on Real Architectures''', and the wiki pages are very close to those of the previous year. <ref name=A44 /> adds a chapter on MESI and ARM11 and Cortex-A9 MPCore, which are in fashion these days. It also presents a chapter on Instruction Prefetching and another in Word Invalidation. <ref name=C1 /> is a very good page and article with an excellent coverage.		Now in Spring 2012, <ref name=A43 /> and <ref name=A44 /> develop a similar topic as <ref name=A42 />, '''MSI, MESI, MESIF, And MOESI Protocols on Real Architectures''', and the wiki pages are very close to those of the previous year. <ref name=A44 /> adds a chapter on MESI and ARM11 and Cortex-A9 MPCore, which are in fashion these days. It also presents a chapter on Instruction Prefetching and another in Word Invalidation. <ref name=D1 /> is a very good page and article with an excellent coverage.

	==Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations==		==Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations==

Pmfernan: /* MSI, MESI, MESIF, And MOESI Protocols on Real Architectures */

2012-05-10T21:08:07Z

MSI, MESI, MESIF, And MOESI Protocols on Real Architectures

← Older revision		Revision as of 21:08, 10 May 2012
Line 90:		Line 90:
	The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.		The first section in this chapter is from Spring 2011 and is titled '''Introduction To Bus-Based Cache Coherence In Real Machines'''. While <ref name=A41 /> describes well all the coherence protocols, <ref name=A42 /> makes a point to associate them to the architectures and vendors they were developed for. It first presents the common bus architecture in SMP systems and summarizing some of the more commons Cache Coherence Protocols, like MSI, MESI, MESIF or MOESI, their states and transitions; and discussing their performance. Following, it goes to describe several architectures, starting with MSI & SGI IRIS 4D Processors, then Synapse protocol and Synapse multiprocessors, MESI and Intel Processors, with a brief explanation of the Intel processor architecture and evolution; and the MOESI & AMD Processors, with the Opteron and Phenom example architectures, and other particularities, performance enhancements and optimizations of the AMD64 family of processors. It ends with Dragon Protocol & Xerox Dragon Processors to give pass to discussions on Cache Coherence Power Utilization and discussing possible power savings that can be obtained using Snoop Filtering, eliminating unnecessary snoops, with techniques like Serial Snooping and Jetty.
	==MSI, MESI, MESIF, And MOESI Protocols on Real Architectures==		==MSI, MESI, MESIF, And MOESI Protocols on Real Architectures==
	Now in Spring 2012, <ref name=A43 /> and <ref name=A44 /> develop a similar topic as <ref name=A42 />, '''MSI, MESI, MESIF, And MOESI Protocols on Real Architectures''', and the wiki pages are very close to those of the previous year. <ref name=A44 /> adds a chapter on MESI and ARM11 and Cortex-A9 MPCore, which are in fashion these days. It also presents a chapter on Instruction Prefetching and another in Word Invalidation.		Now in Spring 2012, <ref name=A43 /> and <ref name=A44 /> develop a similar topic as <ref name=A42 />, '''MSI, MESI, MESIF, And MOESI Protocols on Real Architectures''', and the wiki pages are very close to those of the previous year. <ref name=A44 /> adds a chapter on MESI and ARM11 and Cortex-A9 MPCore, which are in fashion these days. It also presents a chapter on Instruction Prefetching and another in Word Invalidation. <ref name=C1 /> is a very good page and article with an excellent coverage.

	==Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations==		==Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations==
	Last section takes on '''Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations'''. <ref name=A45 /> introduces the coherence protocols, which take care of making sure that changes in a cache are propagated to the others. Main issue, they state, is that all this transient of information brings extra traffic to the bus and, hence, congestion. They define then the concept of coherence and the two possible approaches, write-update and write-invalidate protocols. The paper focused then in write-update only protocols, starting with the Xerox-Dragon protocol, which is explained; and then with the DEC Firefly protocol. After this it passes to describe the Adaptive Coherence Protocols, which, given the disadvantages of both write-update and write-invalidate, try to mix them in a hybrid scheme, which is here described, together with the hardware architecture needed ti support it. The Sublock Protocol, a snoopy-based adaptation of the Illinois MESI protocol, is also presented with a description of its mechanisms and advantages of this protocol versus more coarse ones. Finally an enhancement of this technique, the Read-snarfing protocol, is presented as an example, with coding proposals and studies over some particular situations; and some simulations results are also shown.		Last section takes on '''Update And Adaptive Coherence Protocols On Real Architectures, And Power Considerations'''. <ref name=A45 /> introduces the coherence protocols, which take care of making sure that changes in a cache are propagated to the others. Main issue, they state, is that all this transient of information brings extra traffic to the bus and, hence, congestion. They define then the concept of coherence and the two possible approaches, write-update and write-invalidate protocols. The paper focused then in write-update only protocols, starting with the Xerox-Dragon protocol, which is explained; and then with the DEC Firefly protocol. After this it passes to describe the Adaptive Coherence Protocols, which, given the disadvantages of both write-update and write-invalidate, try to mix them in a hybrid scheme, which is here described, together with the hardware architecture needed ti support it. The Sublock Protocol, a snoopy-based adaptation of the Illinois MESI protocol, is also presented with a description of its mechanisms and advantages of this protocol versus more coarse ones. Finally an enhancement of this technique, the Read-snarfing protocol, is presented as an example, with coding proposals and studies over some particular situations; and some simulations results are also shown.

Pmfernan: /* Chapter 8: Bus-Based Coherent Multiprocessors */

2012-05-10T20:54:57Z

Chapter 8: Bus-Based Coherent Multiprocessors

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	=Chapter 8: Bus-Based Coherent Multiprocessors=		=Chapter 8: Bus-Based Coherent Multiprocessors=
	Pages in this chapter: <ref name=A41>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_cl Spring_2011/ch8_cl]</ref><ref name=A42>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_mc Spring_2011/ch8_mc]</ref> <ref name=A43>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_cj Spring_2012/8a_cj]</ref><ref name=A44>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_fu Spring_2012/8a_fu]</ref> <ref name=A45>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8b_va Spring_2012/8b_va]</ref><ref name=C1>[http://expertiza.csc.ncsu.edu/wiki/index.php/User:Stchen#Introduction_to_Update_and_Adaptive_Coherence_Protocols_on_Real_Architectures Spring_2012/Stchen]</ref><ref name=D1>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2010/8a_sk Spring_2010/8a_sk]</ref>		Pages in this chapter: <ref name=A41>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_cl Spring_2011/ch8_cl]</ref><ref name=A42>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_mc Spring_2011/ch8_mc]</ref> <ref name=A43>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_cj Spring_2012/8a_cj]</ref><ref name=A44>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_fu Spring_2012/8a_fu]</ref> <ref name=A45>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8b_va Spring_2012/8b_va]</ref><ref name=C1>[http://expertiza.csc.ncsu.edu/wiki/index.php/User:Stchen#Introduction_to_Update_and_Adaptive_Coherence_Protocols_on_Real_Architectures Spring_2012/Stchen]</ref><ref name=D1>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2010/8a_sk Spring_2010/8a_sk]</ref>


	This dense chapter of the Solihin<ref name=A1 /> talks about bus-based architecture and how to assure coherence in a multiprocessor system that uses it. It defines the bus, its characteristics and transactions and the design choices that we can have. Then it goes into bus arbitration and snooping-based coherence and describes the protocols that use it, like MSI, MESI, MOESI, Dragon or Firefly. While the first set of wikis connect those protocols with the real machine implementations they were develop for, the lasts go deeper into implementation issues and, being an topic of great relevance lately, power schemes.		This dense chapter of the Solihin<ref name=A1 /> talks about bus-based architecture and how to assure coherence in a multiprocessor system that uses it. It defines the bus, its characteristics and transactions and the design choices that we can have. Then it goes into bus arbitration and snooping-based coherence and describes the protocols that use it, like MSI, MESI, MOESI, Dragon or Firefly. While the first set of wikis connect those protocols with the real machine implementations they were develop for, the lasts go deeper into implementation issues and, being an topic of great relevance lately, power schemes.

Pmfernan: /* Chapter 8: Bus-Based Coherent Multiprocessors */

2012-05-10T20:54:43Z

Chapter 8: Bus-Based Coherent Multiprocessors

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	=Chapter 8: Bus-Based Coherent Multiprocessors=		=Chapter 8: Bus-Based Coherent Multiprocessors=
	Pages in this chapter: <ref name=A41>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_cl Spring_2011/ch8_cl]</ref><ref name=A42>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_mc Spring_2011/ch8_mc]</ref> <ref name=A43>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_cj Spring_2012/8a_cj]</ref><ref name=A44>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_fu Spring_2012/8a_fu]</ref> <ref name=A45>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8b_va Spring_2012/8b_va]</ref><ref name=C1>[http://expertiza.csc.ncsu.edu/wiki/index.php/User:Stchen#Introduction_to_Update_and_Adaptive_Coherence_Protocols_on_Real_Architectures Spring_2012/Stchen]</ref>		Pages in this chapter: <ref name=A41>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_cl Spring_2011/ch8_cl]</ref><ref name=A42>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_mc Spring_2011/ch8_mc]</ref> <ref name=A43>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_cj Spring_2012/8a_cj]</ref><ref name=A44>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_fu Spring_2012/8a_fu]</ref> <ref name=A45>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8b_va Spring_2012/8b_va]</ref><ref name=C1>[http://expertiza.csc.ncsu.edu/wiki/index.php/User:Stchen#Introduction_to_Update_and_Adaptive_Coherence_Protocols_on_Real_Architectures Spring_2012/Stchen]</ref><ref name=D1>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2010/8a_sk Spring_2010/8a_sk]</ref>


	This dense chapter of the Solihin<ref name=A1 /> talks about bus-based architecture and how to assure coherence in a multiprocessor system that uses it. It defines the bus, its characteristics and transactions and the design choices that we can have. Then it goes into bus arbitration and snooping-based coherence and describes the protocols that use it, like MSI, MESI, MOESI, Dragon or Firefly. While the first set of wikis connect those protocols with the real machine implementations they were develop for, the lasts go deeper into implementation issues and, being an topic of great relevance lately, power schemes.		This dense chapter of the Solihin<ref name=A1 /> talks about bus-based architecture and how to assure coherence in a multiprocessor system that uses it. It defines the bus, its characteristics and transactions and the design choices that we can have. Then it goes into bus arbitration and snooping-based coherence and describes the protocols that use it, like MSI, MESI, MOESI, Dragon or Firefly. While the first set of wikis connect those protocols with the real machine implementations they were develop for, the lasts go deeper into implementation issues and, being an topic of great relevance lately, power schemes.

Pmfernan: /* Chapter 8: Bus-Based Coherent Multiprocessors */

2012-05-09T17:56:50Z

Chapter 8: Bus-Based Coherent Multiprocessors

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	=Chapter 8: Bus-Based Coherent Multiprocessors=		=Chapter 8: Bus-Based Coherent Multiprocessors=
	Pages in this chapter: <ref name=A41>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_cl Spring_2011/ch8_cl]</ref><ref name=A42>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_mc Spring_2011/ch8_mc]</ref> <ref name=A43>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_cj Spring_2012/8a_cj]</ref><ref name=A44>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_fu Spring_2012/8a_fu]</ref> <ref name=A45>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8b_va Spring_2012/8b_va]</ref>		Pages in this chapter: <ref name=A41>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_cl Spring_2011/ch8_cl]</ref><ref name=A42>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch8_mc Spring_2011/ch8_mc]</ref> <ref name=A43>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_cj Spring_2012/8a_cj]</ref><ref name=A44>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8a_fu Spring_2012/8a_fu]</ref> <ref name=A45>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/8b_va Spring_2012/8b_va]</ref><ref name=C1>[http://expertiza.csc.ncsu.edu/wiki/index.php/User:Stchen#Introduction_to_Update_and_Adaptive_Coherence_Protocols_on_Real_Architectures Spring_2012/Stchen]</ref>

	This dense chapter of the Solihin<ref name=A1 /> talks about bus-based architecture and how to assure coherence in a multiprocessor system that uses it. It defines the bus, its characteristics and transactions and the design choices that we can have. Then it goes into bus arbitration and snooping-based coherence and describes the protocols that use it, like MSI, MESI, MOESI, Dragon or Firefly. While the first set of wikis connect those protocols with the real machine implementations they were develop for, the lasts go deeper into implementation issues and, being an topic of great relevance lately, power schemes.		This dense chapter of the Solihin<ref name=A1 /> talks about bus-based architecture and how to assure coherence in a multiprocessor system that uses it. It defines the bus, its characteristics and transactions and the design choices that we can have. Then it goes into bus arbitration and snooping-based coherence and describes the protocols that use it, like MSI, MESI, MOESI, Dragon or Firefly. While the first set of wikis connect those protocols with the real machine implementations they were develop for, the lasts go deeper into implementation issues and, being an topic of great relevance lately, power schemes.
	==Introduction To Bus-Based Cache Coherence In Real Machines==		==Introduction To Bus-Based Cache Coherence In Real Machines==