CSC/ECE 506 Spring 2012/6b am - Revision history

Sbasu3: /* Universal read/write Bufferhttp://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=342629&tag=1 */

2012-03-06T22:40:51Z

Universal read/write Bufferhttp://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=342629&tag=1

← Older revision		Revision as of 22:40, 6 March 2012
Line 85:		Line 85:
	[[Image:Universal Read Write Buffer.png\|thumb\|right\|300px\|Figure 5: Universal Read/Write Buffer [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/6b_dm#cite_note-4 5]]]		[[Image:Universal Read Write Buffer.png\|thumb\|right\|300px\|Figure 5: Universal Read/Write Buffer [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/6b_dm#cite_note-4 5]]]

	In this approach, a shared bus controller resides in between the local bus and memory bus, where local bus is connected to all private caches of the processors (illustrated in Figure 5). This technique supports multiple processors with same or different coherence protocols like; MSI, MESI and MOESI write invalidate strategy. Shared bus controller consists of the local bus controller, the data buffer and the address buffer. Each private cache provides two bit tri-state signals to the local bus – '''INTERVENE''' and '''SHARE'''.		In this approach, a shared bus controller resides in between the local bus and memory bus, where local bus is connected to all private caches of the processors (illustrated in [http://expertiza.csc.ncsu.edu/wiki/index.php/File:Universal_Read_Write_Buffer.png Figure 5]). This technique supports multiple processors with same or different coherence protocols like; MSI, MESI and MOESI write invalidate strategy. Shared bus controller consists of the local bus controller, the data buffer and the address buffer. Each private cache provides two bit tri-state signals to the local bus – '''INTERVENE''' and '''SHARE'''.

	# INTERVENE is asserted when any cache wants to provide a valid data to other caches.		# INTERVENE is asserted when any cache wants to provide a valid data to other caches.

Acdeshpa: /* Maintaining Sequential Consistency */

2012-03-06T05:18:53Z

Maintaining Sequential Consistency

← Older revision		Revision as of 05:18, 6 March 2012
Line 172:		Line 172:
	When operating as a part of a multiprocessor, it is not enough to check dependencies between the writes only at the local level. As data is shared and the course of events in different processors may affect the outcomes of each other, it has to be ensured that the sequence of writes is preserved between the multiple processors.		When operating as a part of a multiprocessor, it is not enough to check dependencies between the writes only at the local level. As data is shared and the course of events in different processors may affect the outcomes of each other, it has to be ensured that the sequence of writes is preserved between the multiple processors.

	<blockquote>“A system is said to be sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operation of each individual processor appear in this sequence in the order specified by its program.”<ref>http://www.cs.jhu.edu/~gyn/publications/memorymodels/node6.html</ref></blockquote>		<blockquote>“A system is said to be sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operation of each individual processor appear in this sequence in the order specified by its program.”<ref name="node6">http://www.cs.jhu.edu/~gyn/publications/memorymodels/node6.html</ref></blockquote>

	As mentioned earlier, the sequential ordering policy applied has a strong bearing on the write-buffer management policy. Buffer management refers to the order in which multiple buffer requests are treated. In most cases, the requests are treated in a strict FIFO order, while in some cases requests may be allowed to pass each other in the buffer. This is referred to as jockeying<ref name="dubois" />. Jockeying is often permitted between memory requests for different memory words, but is not permitted between requests with the same memory word. This approach is called restricted jockeying<ref name="dubois" />.		As mentioned earlier, the sequential ordering policy applied has a strong bearing on the write-buffer management policy. Buffer management refers to the order in which multiple buffer requests are treated. In most cases, the requests are treated in a strict FIFO order, while in some cases requests may be allowed to pass each other in the buffer. This is referred to as jockeying<ref name="dubois" />. Jockeying is often permitted between memory requests for different memory words, but is not permitted between requests with the same memory word. This approach is called restricted jockeying<ref name="dubois" />.
Line 187:		Line 187:

	===Weak Ordering===		===Weak Ordering===
	In weakly ordered systems, processors can issue shared memory accesses without waiting for previous accesses to be performed. Jockeying is allowed in the buffers, and accesses can pass each other out of serial program order. However, there is necessity to maintain consistency while accessing the synchronization variables. Synchronization variables are the variables that are responsible in the multi-program to maintain concurrency between processes running on separate processors<ref~~>http://www.cs.jhu.edu/~gyn/publications/memorymodels/~~node6~~.html<~~/~~ref~~>. Needless to say, as accesses can pass each other, the efficiency of the weakly ordered systems is much higher than the strongly ordered systems, but the implementation is much more complex, for the necessity to maintain the correctness of the program.		In weakly ordered systems, processors can issue shared memory accesses without waiting for previous accesses to be performed. Jockeying is allowed in the buffers, and accesses can pass each other out of serial program order. However, there is necessity to maintain consistency while accessing the synchronization variables. Synchronization variables are the variables that are responsible in the multi-program to maintain concurrency between processes running on separate processors<ref name="node6" />. Needless to say, as accesses can pass each other, the efficiency of the weakly ordered systems is much higher than the strongly ordered systems, but the implementation is much more complex, for the necessity to maintain the correctness of the program.

Acdeshpa: /* Coherence Models */

2012-03-06T05:17:35Z

Coherence Models

← Older revision		Revision as of 05:17, 6 March 2012
Line 39:		Line 39:
	<blockquote>"A memory scheme is coherent if the value returned on a LOAD instruction is always the value given by the latest STORE instruction with the same address."<ref name="dubois" /></blockquote>		<blockquote>"A memory scheme is coherent if the value returned on a LOAD instruction is always the value given by the latest STORE instruction with the same address."<ref name="dubois" /></blockquote>

	The two conventional models followed to attain this objective are the snoopy-bus protocol and the directory-based coherence protocol<ref>http://www.csl.cornell.edu/~heinrich/dissertation/ChapterTwo.pdf</ref>. The directory-based protocol is used for distributed memory systems, in which every processor keeps track of what data is being stored using a directory entry. In the snoopy-bus protocol, every processor monitors the reads and writes that are being serviced by the memory bus. The read and write requests can be broadcast on the bus for all the processors to respond based on whether or not they are in possession of that data in their cache.		The two conventional models followed to attain this objective are the snoopy-bus protocol and the directory-based coherence protocol<ref name="chapter-two">http://www.csl.cornell.edu/~heinrich/dissertation/ChapterTwo.pdf</ref>. The directory-based protocol is used for distributed memory systems, in which every processor keeps track of what data is being stored using a directory entry. In the snoopy-bus protocol, every processor monitors the reads and writes that are being serviced by the memory bus. The read and write requests can be broadcast on the bus for all the processors to respond based on whether or not they are in possession of that data in their cache.

	With the addition of write buffers in the system, it is now essential that a processor be aware of the memory transactions occurring not only at the caches of other processors, but also in their write buffers. The snoopy bus protocol can maintain coherence between multiple write buffers by communicating using one of the two protocols explained below.		With the addition of write buffers in the system, it is now essential that a processor be aware of the memory transactions occurring not only at the caches of other processors, but also in their write buffers. The snoopy bus protocol can maintain coherence between multiple write buffers by communicating using one of the two protocols explained below.
Line 50:		Line 50:


	Write–update strategy is liable to keep and update unnecessary data in the cache - the least recently used [http://en.wikipedia.org/wiki/Cache_algorithms#Least_Recently_Used (LRU)] algorithm may evict the useful data from the cache and keep the redundant updated data. Most present day processors employ write-invalidate policy because of its ease of implementation<ref~~>http:~~/~~/www.csl.cornell.edu/~heinrich/dissertation/ChapterTwo.pdf</ref~~>. In this article, for write-propagation of all hardware and software based designs we follow the write-invalidate strategy.		Write–update strategy is liable to keep and update unnecessary data in the cache - the least recently used [http://en.wikipedia.org/wiki/Cache_algorithms#Least_Recently_Used (LRU)] algorithm may evict the useful data from the cache and keep the redundant updated data. Most present day processors employ write-invalidate policy because of its ease of implementation<ref name="chapter-two" />. In this article, for write-propagation of all hardware and software based designs we follow the write-invalidate strategy.

	== Coherence in Write Buffers ==		== Coherence in Write Buffers ==

Acdeshpa: /* Conclusions and Observations */

2012-03-06T05:16:14Z

Conclusions and Observations

← Older revision		Revision as of 05:16, 6 March 2012
Line 238:		Line 238:
	==Conclusions and Observations==		==Conclusions and Observations==

	Although SSB and ASO are not essentially means by which write buffers communicate in the multiprocessor systems, these are the techniques that are necessary for complete utilization of write buffer hardware when using weak ordering approaches, like TSO. Interested reader may read more about these two schemes in <ref~~>http://www.eecg.toronto.edu/~moshovos/research/~~store-wait-free~~.pdf<~~/~~ref~~>.		Although SSB and ASO are not essentially means by which write buffers communicate in the multiprocessor systems, these are the techniques that are necessary for complete utilization of write buffer hardware when using weak ordering approaches, like TSO. Interested reader may read more about these two schemes in <ref name="store-wait-free" />.
	We can see from the above architectural techniques that using a write buffer in a cache-based multiprocessor system is much helpful in maximizing processor performance by off-loading the store latency to the write-buffer. With hardware and software techniques that take care of issues like the coherence between multiple buffers, capacity limitations of the write buffers and the ordering policy that is followed while implementation, write buffering can be a very strong technique to improve the performance of a multiprocessor system.		We can see from the above architectural techniques that using a write buffer in a cache-based multiprocessor system is much helpful in maximizing processor performance by off-loading the store latency to the write-buffer. With hardware and software techniques that take care of issues like the coherence between multiple buffers, capacity limitations of the write buffers and the ordering policy that is followed while implementation, write buffering can be a very strong technique to improve the performance of a multiprocessor system.

	=='''References'''==		=='''References'''==
	<references/>		<references/>

Acdeshpa: /* Overcoming Buffer Stallshttp://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf */

2012-03-06T05:15:50Z

Overcoming Buffer Stallshttp://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf

← Older revision		Revision as of 05:15, 6 March 2012
Line 204:		Line 204:
	But strong ordering enforces strict atomicity thus we will get different results based on the execution order between two processors’ instructions.		But strong ordering enforces strict atomicity thus we will get different results based on the execution order between two processors’ instructions.

	==Overcoming Buffer Stalls<ref>http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf</ref>==		==Overcoming Buffer Stalls<ref name="store-wait-free">http://www.eecg.toronto.edu/~moshovos/research/store-wait-free.pdf</ref>==

	Although the write buffer does the job of off-loading the write responsibility and hence the write access latency overhead from processor time, there are certain conditions where the processor performance cannot be improved a beyond a certain point. The processor system needs to be stalled if the write buffer overflows, for example. There are two types of stalls that mainly affect the processor performance :		Although the write buffer does the job of off-loading the write responsibility and hence the write access latency overhead from processor time, there are certain conditions where the processor performance cannot be improved a beyond a certain point. The processor system needs to be stalled if the write buffer overflows, for example. There are two types of stalls that mainly affect the processor performance :
	#Buffer capacity related stalls : The buffer capacity related stalls occur when a write buffer overflows, and the processor cannot buffer any more stores. This occurs during store bursts, which are a number of stores that are requested in quick succession. The ''Scalable Store Buffer''<ref~~>http://www.eecg.toronto.edu/~moshovos/research/~~store-wait-free~~.pdf<~~/~~ref~~> is a technique that aims at overcoming capacity-related stalls.		#Buffer capacity related stalls : The buffer capacity related stalls occur when a write buffer overflows, and the processor cannot buffer any more stores. This occurs during store bursts, which are a number of stores that are requested in quick succession. The ''Scalable Store Buffer''<ref name="store-wait-free" /> is a technique that aims at overcoming capacity-related stalls.
	#Ordering related stalls : Modern processors have the ability to execute speculatively<ref>http://www.pcguide.com/ref/cpu/arch/int/featSpeculative-c.html</ref>, which means that they can execute down a predicted path to save processor time. But there are time when the speculation could go wrong, and the state of the system has to be brought to a true state by draining out all requests down the bad path. This incurs a stall penalty on the processor, as no execution can proceed till the system is rolled back to a non-speculative, true state. ''Atomic Sequence Ordering''<ref~~>http://www.eecg.toronto.edu/~moshovos/research/~~store-wait-free~~.pdf<~~/~~ref~~> is a technique that takes care of the ordering-related stalls.		#Ordering related stalls : Modern processors have the ability to execute speculatively<ref>http://www.pcguide.com/ref/cpu/arch/int/featSpeculative-c.html</ref>, which means that they can execute down a predicted path to save processor time. But there are time when the speculation could go wrong, and the state of the system has to be brought to a true state by draining out all requests down the bad path. This incurs a stall penalty on the processor, as no execution can proceed till the system is rolled back to a non-speculative, true state. ''Atomic Sequence Ordering''<ref name="store-wait-free" /> is a technique that takes care of the ordering-related stalls.

	The two are explained here in brief.		The two are explained here in brief.
Line 214:		Line 214:
	===Scalable Store Buffer (SSB)===		===Scalable Store Buffer (SSB)===

	The SSB as mentioned above is employed to overcome the buffer capacity-related stalls in a write-buffer based system. Conventional buffers follow Total Store Ordering<ref~~>http://www.eecg.toronto.edu/~moshovos/research/~~store-wait-free~~.pdf<~~/~~ref~~> in which store values are forwarded to matching loads, and stores maintain total order of execution. The key architecture changes employed by the SSB are :		The SSB as mentioned above is employed to overcome the buffer capacity-related stalls in a write-buffer based system. Conventional buffers follow Total Store Ordering<ref name="store-wait-free" /> in which store values are forwarded to matching loads, and stores maintain total order of execution. The key architecture changes employed by the SSB are :
	#The store forwarding is performed through L1 cache, so that the CAM look-up within the write buffer to match loads with stores can be done away with.		#The store forwarding is performed through L1 cache, so that the CAM look-up within the write buffer to match loads with stores can be done away with.
	##Thus the L1 cache contains data values that are private to the processor		##Thus the L1 cache contains data values that are private to the processor

Acdeshpa: /* Maintaining Sequential Consistency */

2012-03-06T05:13:35Z

Maintaining Sequential Consistency

← Older revision		Revision as of 05:13, 6 March 2012
Line 174:		Line 174:
	<blockquote>“A system is said to be sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operation of each individual processor appear in this sequence in the order specified by its program.”<ref>http://www.cs.jhu.edu/~gyn/publications/memorymodels/node6.html</ref></blockquote>		<blockquote>“A system is said to be sequentially consistent if the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operation of each individual processor appear in this sequence in the order specified by its program.”<ref>http://www.cs.jhu.edu/~gyn/publications/memorymodels/node6.html</ref></blockquote>

	As mentioned earlier, the sequential ordering policy applied has a strong bearing on the write-buffer management policy. Buffer management refers to the order in which multiple buffer requests are treated. In most cases, the requests are treated in a strict FIFO order, while in some cases requests may be allowed to pass each other in the buffer. This is referred to as jockeying<ref~~>http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-~~dubois/~~p434-dubois.pdf</ref~~>. Jockeying is often permitted between memory requests for different memory words, but is not permitted between requests with the same memory word. This approach is called restricted jockeying<ref~~>http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-~~dubois/~~p434-dubois.pdf</ref~~>.		As mentioned earlier, the sequential ordering policy applied has a strong bearing on the write-buffer management policy. Buffer management refers to the order in which multiple buffer requests are treated. In most cases, the requests are treated in a strict FIFO order, while in some cases requests may be allowed to pass each other in the buffer. This is referred to as jockeying<ref name="dubois" />. Jockeying is often permitted between memory requests for different memory words, but is not permitted between requests with the same memory word. This approach is called restricted jockeying<ref name="dubois" />.

	We will discuss some ordering approaches, and explore how they are significant to write buffer coherence management.		We will discuss some ordering approaches, and explore how they are significant to write buffer coherence management.

Acdeshpa: /* Separate Buffers for Local and Remote Accesseshttp://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf */

2012-03-06T05:12:18Z

Separate Buffers for Local and Remote Accesseshttp://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf

← Older revision		Revision as of 05:12, 6 March 2012
Line 74:		Line 74:
	# For non-bus MP systems, the caches are connected in point-to-point mesh-based or interconnect ring-based topology. When a store is encountered in one of the processors, the shared data is first locked in the shared memory to ensure atomic access, and then the invalidate signal is propagated along the point-to-point interconnect in a decided order. The STORE to shared memory is performed only when the invalidation has been propagated to all the processor caches and buffers. If any processor issues a LOAD on the same address as that is being STOREd, then the LOAD request has to be rejected or buffered to be serviced at a later time, to maintain atomic access to the shared data block.		# For non-bus MP systems, the caches are connected in point-to-point mesh-based or interconnect ring-based topology. When a store is encountered in one of the processors, the shared data is first locked in the shared memory to ensure atomic access, and then the invalidate signal is propagated along the point-to-point interconnect in a decided order. The STORE to shared memory is performed only when the invalidation has been propagated to all the processor caches and buffers. If any processor issues a LOAD on the same address as that is being STOREd, then the LOAD request has to be rejected or buffered to be serviced at a later time, to maintain atomic access to the shared data block.

	====Separate Buffers for Local and Remote Accesses<ref~~>http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-~~dubois~~.pdf<~~/~~ref~~>====		====Separate Buffers for Local and Remote Accesses<ref name="dubois" />====
	[[Image:Separate Invalidate Buffers.png\|thumb\|right\|250px\|Figure 4: Cache based system with separate write-invalidate buffers		[[Image:Separate Invalidate Buffers.png\|thumb\|right\|250px\|Figure 4: Cache based system with separate write-invalidate buffers
	[[http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf]]]]		[[http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf]]]]

	Another approach to maintaining coherence is for every processor to have separate buffers for local data requests and remote data requests. As seen in the [http://expertiza.csc.ncsu.edu/wiki/index.php/File:Separate_Invalidate_Buffers.png Figure 4], every processor has a Local-buffer which queues the local LOADs and STOREs, and a Remote-buffer (also termed Invalidate buffer) that stores the invalidation requests and LOADs coming in from different processors.		Another approach to maintaining coherence is for every processor to have separate buffers for local data requests and remote data requests. As seen in the [http://expertiza.csc.ncsu.edu/wiki/index.php/File:Separate_Invalidate_Buffers.png Figure 4], every processor has a Local-buffer which queues the local LOADs and STOREs, and a Remote-buffer (also termed Invalidate buffer) that stores the invalidation requests and LOADs coming in from different processors.
	In bus-based processor system, this approach makes it difficult to maintain write atomicity, as different invalidate buffers may hold different number of invalidation requests, putting uncertainty on the time to invalidate the concerned data block in the cache. In non-bus based systems, however, this approach is successful in maintaining strong coherence, provided the invalidate signal makes sure that the data is invalidated at a cache before moving on to the next processor (rather than just pushing the invalidate request in the buffers and moving on)<ref~~>http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-~~dubois~~.pdf<~~/~~ref~~>.		In bus-based processor system, this approach makes it difficult to maintain write atomicity, as different invalidate buffers may hold different number of invalidation requests, putting uncertainty on the time to invalidate the concerned data block in the cache. In non-bus based systems, however, this approach is successful in maintaining strong coherence, provided the invalidate signal makes sure that the data is invalidated at a cache before moving on to the next processor (rather than just pushing the invalidate request in the buffers and moving on)<ref name="dubois" />.

	====Universal read/write Buffer<ref>http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=342629&tag=1</ref>====		====Universal read/write Buffer<ref>http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=342629&tag=1</ref>====

Acdeshpa: /* Unique Buffer per Processorhttp://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf */

2012-03-06T05:11:27Z

Unique Buffer per Processorhttp://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf

← Older revision		Revision as of 05:11, 6 March 2012
Line 60:		Line 60:
	In hardware-based protocols accesses to the shared memory are communicated using hardware invalidate signals that are broadcasted to all the processor memories. Hardware support may also be required for a LOAD to be broadcasted to all the caches, so that a read can be performed directly from a remote memory. There are two approaches to maintaining coherence in write buffers and caches for multiprocessor system-		In hardware-based protocols accesses to the shared memory are communicated using hardware invalidate signals that are broadcasted to all the processor memories. Hardware support may also be required for a LOAD to be broadcasted to all the caches, so that a read can be performed directly from a remote memory. There are two approaches to maintaining coherence in write buffers and caches for multiprocessor system-

	====Unique Buffer per Processor<ref~~>http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-~~dubois~~.pdf<~~/~~ref~~>====		====Unique Buffer per Processor<ref name="dubois" />====
	[[Image:Unique Buffer Per Processor.png\|thumb\|right\|250px\|Figure 3: Cache based system with unique buffer per processor		[[Image:Unique Buffer Per Processor.png\|thumb\|right\|250px\|Figure 3: Cache based system with unique buffer per processor
	[[http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf]]]]		[[http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf]]]]

Acdeshpa: /* Coherence Models */

2012-03-06T05:09:49Z

Coherence Models

← Older revision		Revision as of 05:09, 6 March 2012
Line 37:		Line 37:
	==Coherence Models==		==Coherence Models==

	<blockquote>"A memory scheme is coherent if the value returned on a LOAD instruction is always the value given by the latest STORE instruction with the same address."<ref~~>http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-~~dubois~~.pdf<~~/~~ref~~></blockquote>		<blockquote>"A memory scheme is coherent if the value returned on a LOAD instruction is always the value given by the latest STORE instruction with the same address."<ref name="dubois" /></blockquote>

	The two conventional models followed to attain this objective are the snoopy-bus protocol and the directory-based coherence protocol<ref>http://www.csl.cornell.edu/~heinrich/dissertation/ChapterTwo.pdf</ref>. The directory-based protocol is used for distributed memory systems, in which every processor keeps track of what data is being stored using a directory entry. In the snoopy-bus protocol, every processor monitors the reads and writes that are being serviced by the memory bus. The read and write requests can be broadcast on the bus for all the processors to respond based on whether or not they are in possession of that data in their cache.		The two conventional models followed to attain this objective are the snoopy-bus protocol and the directory-based coherence protocol<ref>http://www.csl.cornell.edu/~heinrich/dissertation/ChapterTwo.pdf</ref>. The directory-based protocol is used for distributed memory systems, in which every processor keeps track of what data is being stored using a directory entry. In the snoopy-bus protocol, every processor monitors the reads and writes that are being serviced by the memory bus. The read and write requests can be broadcast on the bus for all the processors to respond based on whether or not they are in possession of that data in their cache.

Acdeshpa: /* Write Buffer Issues in Multiprocessors */

2012-03-06T05:08:50Z

Write Buffer Issues in Multiprocessors

← Older revision		Revision as of 05:08, 6 March 2012
Line 25:		Line 25:


	[[Image:Multiprocessor with WB.png\|thumb\|center\|400px\|Figure 2. Cache- based multiprocessor system with write buffer <ref>[http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf</ref>]]		[[Image:Multiprocessor with WB.png\|thumb\|center\|400px\|Figure 2. Cache- based multiprocessor system with write buffer <ref name="dubois">[http://mprc.pku.cn/mentors/training/ISCAreading/1986/p434-dubois/p434-dubois.pdf</ref>]]

	===The Coherence Problem===		===The Coherence Problem===