CSC/ECE 506 Spring 2012/12b sb - Revision history

Shvemuri at 18:35, 17 April 2013

2013-04-17T18:35:12Z

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	==== Tilera ====		==== Tilera ====

	~~The~~ [http://www.tilera.com/products/processors Tilera TileGx, TilePro, and Tile64] ~~use~~ the ~~Tilera’s iMesh™~~ on-chip ~~network~~. The iMesh™ consists of five 8x8 independent mesh networks with two 32-bit unidirectional links per channel. It provides a bisection bandwidth of 320GB/s.		Tilera [http://www.tilera.com/products/processors Tilera TileGx, TilePro, and Tile64] is a fabless semiconductor company that has developed a "tile processor" whereby the fabrication of the multi-processor device is greatly simplified by the placement of processor "tiles" on the die. The technology behind this innovation is iMesh, which is the name of the on-chip interconnection technology used in the Tile Processor's architecture<ref name="Tilera">"On-Chip Interconnection Architecture of the Tile Processor," Wentzlaff, et al. 2007. IEEE Xplore.</ref>. The iMesh™ consists of five 8x8 independent mesh networks with two 32-bit unidirectional links per channel. The Tile Processor is innovative due to its highly scalable implementation of an on-chip network that utilizes 2D meshes. These are physically organized (as opposed to logically organized) due to design considerations when scaling and laying out new designs.It provides a bisection bandwidth of 320GB/s.

	The tiles that conform the Tilera designs contain a complete processor with L1 and L2 caches. And each one can run an operating system in an independent manner or several tiles can run, together as a whole, an operating system like SMP Linux, for example.		The tiles that conform the Tilera designs contain a complete processor with L1 and L2 caches. And each one can run an operating system in an independent manner or several tiles can run, together as a whole, an operating system like SMP Linux, for example.

Smalexa2: /* CHIPPER (Cheap-Interconnect Partially Permuting Router) */

2012-04-26T05:52:53Z

CHIPPER (Cheap-Interconnect Partially Permuting Router)

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	==== CHIPPER (Cheap-Interconnect Partially Permuting Router) ====		==== CHIPPER (Cheap-Interconnect Partially Permuting Router) ====

	This protocol was designed to address inefficient port allocation in the BLESS protocol. A permutation network directs deflected flits to free output ports. By limiting the requirements so that only that the highest-priority flit obtains its request, we can prevent livelock. In the case of contention, arbitration logic chooses a winning flit. It does this ~~using a novel scheme, it is possible to pick~~ a single packet, and prioritize that packet globally above all other packets for long enough that its delivery is ensured. Every packet in the system eventually receives this special status, so every packet is eventually delivered (the Golden Packet scheme).[[#References\|[11]]]		This protocol was designed to address inefficient port allocation in the BLESS protocol. A permutation network directs deflected flits to free output ports. By limiting the requirements so that only that the highest-priority flit obtains its request, we can prevent livelock. In the case of contention, arbitration logic chooses a winning flit. It does this by choosing a single packet, and prioritize that packet globally above all other packets for long enough that its delivery is ensured. Every packet in the system eventually receives this special status, so every packet is eventually delivered (the Golden Packet scheme).[[#References\|[11]]]

	==== Dimension-order Routing ====		==== Dimension-order Routing ====

Smalexa2: /* Logic Based Distributed Routing (LBDR) */

2012-04-26T05:51:30Z

Logic Based Distributed Routing (LBDR)

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	There are several variations of LBDR		There are several variations of LBDR

	''' LBDRe ''' - ~~Uses extended path information~~ to ~~when calculating current routing~~ hops ~~by modeling up~~ to the next ~~two potential hops~~		''' LBDRe ''' - This variation models up to two future hops before deciding where to send the packet next.

	''' uLBDR (Universal LBDR) ''' - ~~The~~ adds multicast support to the protocol		''' uLBDR (Universal LBDR) ''' - This variation adds packet multicast support to the protocol.

	''' bLBDR ''' - ~~Adds~~ the ability to broadcast messages to only certain regions of the network.		''' bLBDR ''' - This variation adds the ability to broadcast messages to only certain regions (segments) of the network.

	==== Bufferless Deflection Routing (BLESS protocol) ====		==== Bufferless Deflection Routing (BLESS protocol) ====

Smalexa2: /* Deadlock and Livelock */

2012-04-26T05:43:05Z

Deadlock and Livelock

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	====Deadlock and Livelock====		====Deadlock and Livelock====

	Deadlock and livelock are two separate situations that may occur during routing, ~~they~~ are defined as follows:		Deadlock and livelock are two separate situations that may occur during routing, both resulting in packets never reaching their destination. They are defined as follows:

	''' Deadlock ''' is defined as a situation where there are activities (e.g., messages) each waiting for another to finish something.[[#References\|[8]]] Since a waiting activity cannot finish, the messages are deadlocked.		''' Deadlock ''' is defined as a situation where there are activities (e.g., messages) each waiting for another to finish something.[[#References\|[8]]] Since a waiting activity cannot finish, the messages are deadlocked. This is analogous to the [http://en.wikipedia.org/wiki/Dining_philosophers_problem Dining Philosophers Problem], each deadlocked message is waiting on the result of another deadlocked message, and none are able to reach their destination.

	''' Livelock ''' is defined as a situation where a message can move from node to node but will never reach their destination node.[[#References\|[8]]]		''' Livelock ''' is defined as a situation where a message can move from node to node but will never reach their destination node.[[#References\|[8]]] This is similar to deadlock in that the message never reaches its destination, but the message is still able to travel through portions of the network, making hops but never reaching its target. This is analogous to a process spinning while waiting, the process itself is doing meaningless work but it is still active.

	----		----

Smalexa2: /* Quiz */

2012-04-26T05:31:44Z

Quiz

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	b) False		b) False


	7. Livelock is necessary to maintain coherence in routing protocols.		7. Livelock is necessary to maintain coherence in routing protocols.
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	b) False		b) False


	8. Dimension Order routing		8. Dimension Order routing
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	c) uses routing tables to find the packet destination.		c) uses routing tables to find the packet destination.


	9. Source routing		9. Source routing
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	c) all of the above		c) all of the above

	10.
			10. Store and forward routing

			a) requires the entire message to be broken into regular sized pieces and sent over the network

			b) is an optimal routing protocol

			c) buffers the entire message in each node along the route before sending it to the next node

Smalexa2: /* Quiz */

2012-04-26T05:28:26Z

Quiz

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	c) uses routing tables to find the packet destination.		c) uses routing tables to find the packet destination.

	9.		9. Source routing

			a) includes information in the packet about the destination node

			b) uses routing information calculated by the sending node

			c) all of the above

	10.		10.

Smalexa2: /* Quiz */

2012-04-26T05:26:38Z

Quiz

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	b) False		b) False

	8.		8. Dimension Order routing

			a) is only possible with 2D mesh-based topologies.

			b) attempts to route all packets in one dimension before starting another.

			c) uses routing tables to find the packet destination.

	9.		9.

	10.		10.

Smalexa2: /* Quiz */

2012-04-26T05:24:36Z

Quiz

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	6.		6. A deterministic routing scheme uses algorithms to determine the most advantageous path to the target node.

	7.		a) True

			b) False

			7. Livelock is necessary to maintain coherence in routing protocols.

			a) True

			b) False

	8.		8.

Birocam: /* Quiz */

2012-04-25T01:24:35Z

Quiz

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	== Quiz ==		== Quiz ==
	1. Advantage of 2-D Mesh		1. Advantage of 2-D Mesh

	a) simple design		a) simple design

	b) cumbersome design		b) cumbersome design

	c) degree is the same for all nodes		c) degree is the same for all nodes


	2. Diameter is		2. Diameter is

	a) minimum hop count		a) minimum hop count

	b) maximum hop count		b) maximum hop count

	c) number of neighbors		c) number of neighbors


	3. SOC stands for		3. SOC stands for

	a) System of Chips		a) System of Chips

	b) Switch of Cores		b) Switch of Cores

	c) System on a Chip		c) System on a Chip


	4. In a direct topology,		4. In a direct topology,

	a) each node contains a network interface acting as a router in order to transfer information		a) each node contains a network interface acting as a router in order to transfer information

	b) there are nodes that act as routers		b) there are nodes that act as routers

	c) only one node is a computational nodes		c) only one node is a computational nodes


	5. The Single-Chip Cloud Computer contains		5. The Single-Chip Cloud Computer contains

	a) an 8x10 mesh		a) an 8x10 mesh

	b) a 64-router mesh network		b) a 64-router mesh network

	c) a 24-router mesh network		c) a 24-router mesh network


	6.		6.

Birocam: /* Quiz */

2012-04-25T01:23:07Z

Quiz

← Older revision		Revision as of 01:23, 25 April 2012
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	== Quiz ==		== Quiz ==
	1.		1. Advantage of 2-D Mesh
			a) simple design
			b) cumbersome design
			c) degree is the same for all nodes

	2.		2. Diameter is
			a) minimum hop count
			b) maximum hop count
			c) number of neighbors

	3.		3. SOC stands for
			a) System of Chips
			b) Switch of Cores
			c) System on a Chip

	4.		4. In a direct topology,
			a) each node contains a network interface acting as a router in order to transfer information
			b) there are nodes that act as routers
			c) only one node is a computational nodes

	5.		5. The Single-Chip Cloud Computer contains
			a) an 8x10 mesh
			b) a 64-router mesh network
			c) a 24-router mesh network

	6.		6.