CSC/ECE 506 Spring 2012/12b jh - Revision history

Jdhartle at 06:01, 17 April 2012

2012-04-17T06:01:48Z

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	<h2>Tile Processor</h2>		<h2>Tile Processor</h2>
	Another way to approach the scaling problem is to use several 2-D mesh networks that are each specialized for a different use. For example, Tilera's Tile Processor uses iMesh, an interconnect network that consists of five 2-D mesh networks, each focusing on a different type of communication (to main memory, to I/O devices, communication between cores). Using multiple mesh networks increases the total bandwidth available to the multiprocessor network - iMesh provides 1.28 terabits per second (Tbps) in and out of a single core.<sup>28</sup>		<p>
			Another way to approach the scaling problem is to use several 2-D mesh networks that are each specialized for a different use. For example, Tilera's Tile Processor uses iMesh, an interconnect network that consists of five 2-D mesh networks, each focusing on a different type of communication (to main memory, to I/O devices, communication between cores). Using multiple mesh networks increases the total bandwidth available to the multiprocessor network - iMesh provides 1.28 terabits per second (Tbps) in and out of a single core. <sup>28</sup>
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Jdhartle at 05:59, 17 April 2012

2012-04-17T05:59:52Z

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	<h1>On-chip Interconnects</h1>		<h1>On-chip Interconnects</h1>
	<p>		<p>
	In order to continue advancing in accordance with Moore's Law, multiprocessors are expected to continue the trend of increasing numbers of processors on a single chip. Current cutting-edge multiprocessors like the Intel Terascale chip have as many as 80 cores, and this is projected to continue to scale until hundreds of cores are implemented on a single piece of silicon. ~~(cite)~~		In order to continue advancing in accordance with Moore's Law, multiprocessors are expected to continue the trend of increasing numbers of processors on a single chip. Current cutting-edge multiprocessors like the Intel Terascale chip have as many as 80 cores, and this is projected to continue to scale until hundreds of cores are implemented on a single piece of silicon. <sup>25</sup>
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	[[File:mec.png]]		[[File:mec.png]]
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			<h2>Tile Processor</h2>
			Another way to approach the scaling problem is to use several 2-D mesh networks that are each specialized for a different use. For example, Tilera's Tile Processor uses iMesh, an interconnect network that consists of five 2-D mesh networks, each focusing on a different type of communication (to main memory, to I/O devices, communication between cores). Using multiple mesh networks increases the total bandwidth available to the multiprocessor network - iMesh provides 1.28 terabits per second (Tbps) in and out of a single core.<sup>28</sup>
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			<p>
			A clear benefit to using multiple on-chip interconnect networks is the potential for specialization. By splitting the interconnection into several networks, the Tile Architecture can optimize each network for a different task. This improves performance when the multiprocessor is being used to run programs with varied requirements.
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			[[File:Tile.png]]
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	<h1>Routing</h1>		<h1>Routing</h1>

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	[24] http://en.wikipedia.org/wiki/LAN		[24] http://en.wikipedia.org/wiki/LAN
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			[25] http://www.cs.utexas.edu/~bgrot/docs/CMP-MSI_08.pdf
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			[26] http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4341445
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			[27] http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1639301
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			[28] http://www.eecg.toronto.edu/~enright/tilera.pdf

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Jdhartle at 05:34, 17 April 2012

2012-04-17T05:34:11Z

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	<h2>Multidrop Express Channels</h2>		<h2>Multidrop Express Channels</h2>
	One potential solution uses express channels between cores that are physically distant, to reduce the total number of hops. In the following 4x4 grid, any two cores can be connected using only two hops (as opposed to a worst case of six hops in a regular 4x4 mesh). This method also scales well: going from 4x4 to 8x8 will double the number of hops required. This is far better than even an optimized 2-D solution like the flattened butterfly, which when going from 4x4 to 8x8 quadruples the number of hops required from 4 to 16.		One potential solution uses express channels between cores that are physically distant, to reduce the total number of hops. In the following 4x4 grid, any two cores can be connected using only two hops (as opposed to a worst case of six hops in a regular 4x4 mesh). This method also scales well: going from 4x4 to 8x8 will double the number of hops required. This is far better than even an optimized 2-D solution like the flattened butterfly, which when going from 4x4 to 8x8 quadruples the number of hops required from 4 to 16.
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	[[File:mec.png]]		[[File:mec.png]]
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Jdhartle at 05:33, 17 April 2012

2012-04-17T05:33:21Z

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 From the figure above, the 6-D hypercube demonstrates the most cost effective choice on this particular network setup. Although the 6-D hypercube costs more because it needs more links and ports, it provides higher bandwidth, which can offset the higher cost. The high dimensional torii also perform well, but cannot provide as much bandwidth as the 6-D hypercube. For systems that do not need as much bandwidth, the high-dimensional torii is also a good choice. The butterfly topology is also an alternative, but has lower fault tolerance.
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 <h1>Routing</h1>

Jdhartle at 04:55, 17 April 2012

2012-04-17T04:55:18Z

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	<h1>Interconnection Network Architecture </h1>		<h1>Interconnection Network Architecture </h1>
	~~<br>~~
	<p>		<p>
	Interconnection network is a programmable system that transports data between terminals. All the terminals are connected to the interconnection network. When one terminal wishes to send data to another terminal, terminal one sends a message containing the data into the network and network delivers message to another terminal. The network is programmable because it makes different connections at different points in time. The network is system because it is composed of many components:		Interconnection network is a programmable system that transports data between terminals. All the terminals are connected to the interconnection network. When one terminal wishes to send data to another terminal, terminal one sends a message containing the data into the network and network delivers message to another terminal. The network is programmable because it makes different connections at different points in time. The network is system because it is composed of many components:

Jdhartle at 04:52, 17 April 2012

2012-04-17T04:52:51Z

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	<h1>Interconnection Network Architecture </h1>		<h1>Interconnection Network Architecture </h1>

	~~<h2>Interconnection networks: What? Where? Why?</h2>~~
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	<h2>History of Interconnection Networks</h2>		<h1>History of Interconnection Networks</h1>

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	<br>		<br>
	<h2> Interconnection Network Topology </h2>		<h1> Interconnection Network Topology </h1>
	<p>		<p>
	In a multi-processor system, processors need to communicate with each other and access each other's resources. In order to route data and messages between processors, an interconnection architecture is needed.		In a multi-processor system, processors need to communicate with each other and access each other's resources. In order to route data and messages between processors, an interconnection architecture is needed.

Jdhartle at 04:45, 17 April 2012

2012-04-17T04:45:50Z

← Older revision		Revision as of 04:45, 17 April 2012
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	<br>		<br>
	<h1> Interconnection Network Topology </h1>		<h2> Interconnection Network Topology </h2>
	<p>		<p>
	In a multi-processor system, processors need to communicate with each other and access each other's resources. In order to route data and messages between processors, an interconnection architecture is needed.		In a multi-processor system, processors need to communicate with each other and access each other's resources. In order to route data and messages between processors, an interconnection architecture is needed.
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	<br>		<br>
	<h2>Types of Network Topologies </h2>		<h1>Types of Network Topologies </h1>

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Jdhartle at 04:45, 17 April 2012

2012-04-17T04:45:05Z

← Older revision		Revision as of 04:45, 17 April 2012
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	<br>		<br>
	<h2> Interconnection Network Topology </h2>		<h1> Interconnection Network Topology </h1>
	<p>		<p>
	In a multi-processor system, processors need to communicate with each other and access each other's resources. In order to route data and messages between processors, an interconnection architecture is needed.		In a multi-processor system, processors need to communicate with each other and access each other's resources. In order to route data and messages between processors, an interconnection architecture is needed.

Jdhartle: Created page with "

Interconnection Network Architecture

Interconnection networks: What? Where? Why?

Interconnection network is a programmable system that transports dat..."

2012-04-12T04:15:33Z

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