CSC/ECE 506 Spring 2012/12b ad - Revision history

Ajdavis7 at 04:30, 25 April 2012

2012-04-25T04:30:41Z

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	'''Answers:''' In numerical question order: 3-4-1-2-2-4-2-1-4-2		'''Answers:''' In numerical question order: 3-4-1-2-2-4-2-1-4-2

			==Further Reading==
			''[http://www.cesr.ncsu.edu/solihin/Main.html Fundamentals of Parallel Computer Architecture]'' by Yan Solihin.

	==References==		==References==
	<references></references>		<references></references>

Ajdavis7 at 04:27, 25 April 2012

2012-04-25T04:27:59Z

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	==Introduction==		==Introduction==
	As the number of processors in multiple-processor systems increases, increasing consideration needs to be given to how those processors communicate. With current technology, for a small number of processors [http://en.wikipedia.org/wiki/Shared_memory shared-memory] arrangements are quite effective. However, as the number of processors increases contention for available resources (memory, bus time, etc) increases, negatively impacting performance of the system. However, keeping these processors all on the same physical piece of hardware is convenient and helps performance due to physical proximity. As such, it is desirable to design hardware where [http://en.wikipedia.org/wiki/Multiprocessing many cores] are part of the same die while allowing for the performance gains possible with [http://en.wikipedia.org/wiki/Computer_network interconnections]. Recently there has been more research into these [http://en.wikipedia.org/wiki/Network_On_Chip on-chip interconnects], and this article will explore the state of those efforts.		As the number of processors in multiple-processor systems increases, increasing consideration needs to be given to how those processors communicate. With current technology, for a small number of processors [http://en.wikipedia.org/wiki/Shared_memory shared-memory] arrangements are quite effective. However, as the number of processors increases contention for available resources (memory, bus time, etc.) increases, negatively impacting performance of the system. However, keeping these processors all on the same physical piece of hardware is convenient and helps performance due to physical proximity. As such, it is desirable to design hardware where [http://en.wikipedia.org/wiki/Multiprocessing many cores] are part of the same die while allowing for the performance gains possible with [http://en.wikipedia.org/wiki/Computer_network interconnections]. Recently there has been more research into these [http://en.wikipedia.org/wiki/Network_On_Chip on-chip interconnects], and this article will explore the state of those efforts.

	==Topologies==		==Topologies==
	The ~~intracacies~~ of semiconductor design and layout afford many different kinds of possible layouts when creating [http://en.wikipedia.org/wiki/Network_topology networking topologies] on [http://en.wikipedia.org/wiki/System-on-a-Chip SoCs]. Specifically, designs need to be amenable to creation on a two-dimension [http://en.wikipedia.org/wiki/Die_(integrated_circuit) substrate], and as such practically limits the use of some more advanced topologies like hypercubes<ref name="GrotKeckler">Grot and Keckler, [http://www.cs.utexas.edu/~bgrot/docs/CMP-MSI_08.pdf Scalable On-Chip Interconnect Topologies]</ref> (circularly-connected mesh).		The intricacies of semiconductor design and layout afford many different kinds of possible layouts when creating [http://en.wikipedia.org/wiki/Network_topology networking topologies] on [http://en.wikipedia.org/wiki/System-on-a-Chip SoCs]. Specifically, designs need to be amenable to creation on a two-dimension [http://en.wikipedia.org/wiki/Die_(integrated_circuit) substrate], and as such practically limits the use of some more advanced topologies like hypercubes<ref name="GrotKeckler">Grot and Keckler, [http://www.cs.utexas.edu/~bgrot/docs/CMP-MSI_08.pdf Scalable On-Chip Interconnect Topologies]</ref> (circularly-connected mesh).

	===Rings===		===Rings===
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	===Flattened Butterfly===		===Flattened Butterfly===
	The flattened butterfly offers the benefits of a tree (less ~~contraints~~ on root-level bandwidth [Solihin 367]) as well as the ability to actually be mapped to a substrate, but because of node concentration<ref name="GrotKeckler"/> the number of channels required for high scalability is cost- and validation-prohibitive.		The flattened butterfly offers the benefits of a tree (less constraints on root-level bandwidth [Solihin 367]) as well as the ability to actually be mapped to a substrate, but because of node concentration<ref name="GrotKeckler"/> the number of channels required for high scalability is cost- and validation-prohibitive.

	===Crossbar Switch===		===Crossbar Switch===
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	==Design Considerations==		==Design Considerations==
	===Energy Consumption===		===Energy Consumption===
	Multi-processor SoCs require additional energy in order to operate the on-chip interconnection hardware like routers. Too, the links between components can introduce increased losses in regards to required voltages and physical arrangement. Indeed, "on-chip network power has been estimated to consume up to 28% of total chip power" due to "channels, router fifos and router crossbar fabrics"<ref name="GrotKeckler" />. Simple topologies use less power due to simpler routers, but the increased number of hops can lead to ~~overal~~ increased power consumption.		Multi-processor SoCs require additional energy in order to operate the on-chip interconnection hardware like routers. Too, the links between components can introduce increased losses in regards to required voltages and physical arrangement. Indeed, "on-chip network power has been estimated to consume up to 28% of total chip power" due to "channels, router fifos and router crossbar fabrics"<ref name="GrotKeckler" />. Simple topologies use less power due to simpler routers, but the increased number of hops can lead to overall increased power consumption.

	===Scalability===		===Scalability===
	Scalability ties back to both energy and cost, but also to engineering constraints as well. ~~Specifcally~~, the architecture needs to be sensitive to the power and heat requirements of the design, as well as the physical die size. Further, the design requires the ability to be fabricated predictably and within reasonable costs. To mitigate some of these factors, concentration of network interfaces can be employed, where a network interface is shared by ~~multipe~~ terminals. Efforts to scale more complicated topologies like the butterfly (into a "flattened" butterfly) have yielded promising results, but at the expense of too much energy expenditure<ref name="GrotKeckler" />.		Scalability ties back to both energy and cost, but also to engineering constraints as well. Specifically, the architecture needs to be sensitive to the power and heat requirements of the design, as well as the physical die size. Further, the design requires the ability to be fabricated predictably and within reasonable costs. To mitigate some of these factors, concentration of network interfaces can be employed, where a network interface is shared by multiple terminals. Efforts to scale more complicated topologies like the butterfly (into a "flattened" butterfly) have yielded promising results, but at the expense of too much energy expenditure<ref name="GrotKeckler" />.

	==Modern Implementations==		==Modern Implementations==

Ajdavis7: /* Quiz */

2012-04-25T04:14:46Z

Quiz

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	# Implementation is incompatible with operating system		# Implementation is incompatible with operating system
	# Attempt to create new de facto programming standards		# Attempt to create new de facto programming standards

			-

	'''Answers:''' In numerical question order: 3-4-1-2-2-4-2-1-4-2		'''Answers:''' In numerical question order: 3-4-1-2-2-4-2-1-4-2

Ajdavis7: /* Quiz */

2012-04-25T04:13:43Z

Quiz

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	# Attempt to create new de facto programming standards		# Attempt to create new de facto programming standards

	'''Answers:'''		'''Answers:''' In numerical question order: 3-4-1-2-2-4-2-1-4-2

	==References==		==References==
	<references></references>		<references></references>

Ajdavis7: /* Quiz */

2012-04-25T04:11:43Z

Quiz

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	# All of the above have similar magnitude in limitation considerations		# All of the above have similar magnitude in limitation considerations

	'''Question 10)''' ~~Why are mesh topologies generally preferred over ring topologies~~?		'''Question 10)''' Which is the best reason CMPs require special programming libraries for best performance?
	# ~~Lower latency~~		# Proprietary code paths for vendor lock-out
	# ~~Cheaper~~ to ~~implement~~		# Allow NoC to more effectively coordinate all cores
	# ~~Lower power consumption~~		# Implementation is incompatible with operating system
	# ~~Better reliability~~		# Attempt to create new de facto programming standards

	'''Answers:''' ~~3-4-1~~		'''Answers:'''

	==References==		==References==
	<references></references>		<references></references>

Ajdavis7: /* Quiz */

2012-04-25T04:03:55Z

Quiz

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	# Around 64-128 cores		# Around 64-128 cores

	'''Question 8)''' ~~Why are mesh topologies generally preferred over ring~~ topologies?		'''Question 8)''' What is a major prohibitive factor of using butterfly topologies in commercial SoC products for a large number of cores?
	# ~~Lower latency~~		# High number of channels
	# ~~Cheaper to implement~~		# High link bandwidth
	# ~~Lower power consumption~~		# High latency on cache misses
	# ~~Better reliability~~		# Low return on investment

	'''Question 9)''' ~~Why are mesh topologies generally preferred over ring topologies~~?		'''Question 9)''' Which of these is the most major factor in limiting physical size in a SoC design?
	# ~~Lower latency~~		# Electrical characteristics (capacitance, noise, clock skew, current, voltage)
	# ~~Cheaper to implement~~		# Process limitations (required equipment, equipment calibration, material purity)
	# ~~Lower power consumption~~		# Power density (process size, material thermal characteristics, number of substrate layers)
	# ~~Better reliability~~		# All of the above have similar magnitude in limitation considerations

	'''Question 10)''' Why are mesh topologies generally preferred over ring topologies?		'''Question 10)''' Why are mesh topologies generally preferred over ring topologies?

Ajdavis7: /* Quiz */

2012-04-25T03:55:09Z

Quiz

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	==Quiz==		==Quiz==
	~~===Questions===~~
	'''Question 1)''' What is another name for the physical substrate of an integrated circuit?		'''Question 1)''' What is another name for the physical substrate of an integrated circuit?
	# Fabric		# Fabric
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	# Notification of Cache Sharing		# Notification of Cache Sharing

	'''Question 6)''' ~~Why are mesh topologies generally preferred over ring~~ topologies?		'''Question 6)''' What is the name of a discrete processing unit used in the construction of certain topologies?
	# ~~Lower latency~~		# Channel
	# ~~Cheaper to implement~~		# Router
	# ~~Lower power consumption~~		# Sentry
	# ~~Better reliability~~		# Tile

	'''Question 7)''' ~~Why are mesh topologies generally preferred over ring topologies~~?		'''Question 7)''' Which choice best characterizes the number of cores in a "medium scale" system?
	# ~~Lower latency~~		# Around 2-8 cores
	# ~~Cheaper to implement~~		# Around 8-16 cores
	# ~~Lower power consumption~~		# Around 32-64 cores
	# ~~Better reliability~~		# Around 64-128 cores

	'''Question 8)''' Why are mesh topologies generally preferred over ring topologies?		'''Question 8)''' Why are mesh topologies generally preferred over ring topologies?

Ajdavis7: /* Quiz */

2012-04-25T03:49:43Z

Quiz

@@ Line 49: / Line 49: @@
 ==Quiz==
 '''Question 1)''' What is another name for the physical substrate of an integrated circuit?
 # Fabric
@@ Line 58: / Line 59: @@
 # Altera
 # ARM
-# Die
+# IBM
 # Cray
@@ Line 66: / Line 67: @@
 # Lower power consumption
 # Better reliability
 ==References==
 <references></references>

Ajdavis7: /* Quiz */

2012-04-25T03:42:04Z

Quiz

@@ Line 49: / Line 49: @@
 ==Quiz==
 ==References==
 <references></references>

Ajdavis7: /* Topologies */

2012-04-25T03:38:04Z

Topologies

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	==Topologies==		==Topologies==
	The intracacies of semiconductor design and layout afford many different kinds of possible layouts when creating [http://en.wikipedia.org/wiki/Network_topology networking topologies] on [http://en.wikipedia.org/wiki/System-on-a-Chip SoCs]. Specifically, designs need to be amenable to creation on a two-dimension [http://en.wikipedia.org/wiki/Die_(integrated_circuit) substrate], and as such practically limits the use of some more advanced topologies like hypercubes <ref name="GrotKeckler">Grot and Keckler, [http://www.cs.utexas.edu/~bgrot/docs/CMP-MSI_08.pdf Scalable On-Chip Interconnect Topologies]</ref>.		The intracacies of semiconductor design and layout afford many different kinds of possible layouts when creating [http://en.wikipedia.org/wiki/Network_topology networking topologies] on [http://en.wikipedia.org/wiki/System-on-a-Chip SoCs]. Specifically, designs need to be amenable to creation on a two-dimension [http://en.wikipedia.org/wiki/Die_(integrated_circuit) substrate], and as such practically limits the use of some more advanced topologies like hypercubes<ref name="GrotKeckler">Grot and Keckler, [http://www.cs.utexas.edu/~bgrot/docs/CMP-MSI_08.pdf Scalable On-Chip Interconnect Topologies]</ref> (circularly-connected mesh).

	===Rings===		===Rings===