CSC/ECE 506 Spring 2011/ch8 mc - Revision history

Chhildeb: /* Definitions */

2011-04-17T23:52:14Z

Definitions

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	* '''Symmetric multiprocessing (SMP)''' - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.		* '''Symmetric multiprocessing (SMP)''' - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.
	* '''Temporal locality''' - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.		* '''Temporal locality''' - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.
	* '''Translation lookaside buffer (TLB)''' - a CPU cache that memory management hardware uses to improve virtual address translation speed.		* '''Translation lookaside buffer (TLB)''' - a CPU cache that memory management hardware uses to improve virtual address translation speed. Converts a virtual address to a physical address.

	=References=		=References=

Chhildeb: /* Definitions */

2011-04-17T23:51:34Z

Definitions

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	* '''Symmetric multiprocessing (SMP)''' - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.		* '''Symmetric multiprocessing (SMP)''' - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.
	* '''Temporal locality''' - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.		* '''Temporal locality''' - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.
			* '''Translation lookaside buffer (TLB)''' - a CPU cache that memory management hardware uses to improve virtual address translation speed.

	=References=		=References=

Chhildeb: /* Special Coherence Considerations in AMD64 architectures */

2011-04-17T23:50:46Z

Special Coherence Considerations in AMD64 architectures

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	Software expects the processor to access the data from physical-page N after the update. However, it is possible for the processor to prefetch the data from physical-page M before the page table for virtual page A is updated. Because the physical-memory references are different, the processor does not recognize them as requiring coherence checking and believes it is safe to prefetch the data from virtual-page A, which is translated into a read from physical page M. Similar behavior can occur when instructions are prefetched from beyond the page table update instruction.		Software expects the processor to access the data from physical-page N after the update. However, it is possible for the processor to prefetch the data from physical-page M before the page table for virtual page A is updated. Because the physical-memory references are different, the processor does not recognize them as requiring coherence checking and believes it is safe to prefetch the data from virtual-page A, which is translated into a read from physical page M. Similar behavior can occur when instructions are prefetched from beyond the page table update instruction.

	In order to prevent errors from occuring, there are special instructions provided by software like INVLPG or MOV CR3 instruction which is executed immediately after the page-table update to ensure that subsequent instruction fetches and data accesses use the correct virtual-page-to-physical-page translation. It is not necessary to perform a {http://en.wikipedia.org/wiki/Translation_lookaside_buffer TLB] invalidation operation preceding the table update.		In order to prevent errors from occuring, there are special instructions provided by software like INVLPG or MOV CR3 instruction which is executed immediately after the page-table update to ensure that subsequent instruction fetches and data accesses use the correct virtual-page-to-physical-page translation. It is not necessary to perform a [http://en.wikipedia.org/wiki/Translation_lookaside_buffer TLB] invalidation operation preceding the table update.

	More information can be found about this in [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf AMD64 Architecture Programmer's manual]		More information can be found about this in [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf AMD64 Architecture Programmer's manual]

Chhildeb: /* Special Coherence Considerations in AMD64 architectures */

2011-04-17T23:50:28Z

Special Coherence Considerations in AMD64 architectures

← Older revision		Revision as of 23:50, 17 April 2011
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	Software expects the processor to access the data from physical-page N after the update. However, it is possible for the processor to prefetch the data from physical-page M before the page table for virtual page A is updated. Because the physical-memory references are different, the processor does not recognize them as requiring coherence checking and believes it is safe to prefetch the data from virtual-page A, which is translated into a read from physical page M. Similar behavior can occur when instructions are prefetched from beyond the page table update instruction.		Software expects the processor to access the data from physical-page N after the update. However, it is possible for the processor to prefetch the data from physical-page M before the page table for virtual page A is updated. Because the physical-memory references are different, the processor does not recognize them as requiring coherence checking and believes it is safe to prefetch the data from virtual-page A, which is translated into a read from physical page M. Similar behavior can occur when instructions are prefetched from beyond the page table update instruction.

	In order to prevent errors from occuring, there are special instructions provided by software like INVLPG or MOV CR3 instruction which is executed immediately after the page-table update to ensure that subsequent instruction fetches and data accesses use the correct virtual-page-to-physical-page translation. It is not necessary to perform a TLB invalidation operation preceding the table update.		In order to prevent errors from occuring, there are special instructions provided by software like INVLPG or MOV CR3 instruction which is executed immediately after the page-table update to ensure that subsequent instruction fetches and data accesses use the correct virtual-page-to-physical-page translation. It is not necessary to perform a {http://en.wikipedia.org/wiki/Translation_lookaside_buffer TLB] invalidation operation preceding the table update.

	More information can be found about this in [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf AMD64 Architecture Programmer's manual]		More information can be found about this in [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf AMD64 Architecture Programmer's manual]

Chhildeb: /* CMP Implementation in Intel Architecture */

2011-04-17T23:49:25Z

CMP Implementation in Intel Architecture

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	=== CMP Implementation in Intel Architecture ===		=== CMP Implementation in Intel Architecture ===

	Let us now see how Intel architecture using the [http://en.wikipedia.org/wiki/MESI_protocol MESI] protocol progressed from a uniprocessor architecture to a Chip MultiProcessor (CMP) using the bus as the interconnect.		Let us now see how Intel architecture using the [http://en.wikipedia.org/wiki/MESI_protocol MESI] protocol progressed from a uniprocessor architecture to a Chip MultiProcessor ([http://en.wikipedia.org/wiki/Multi-core_(computing) CMP]) using the bus as the interconnect.

Chhildeb: /* Introduction to bus-based cache coherence in real machines */

2011-04-17T23:49:01Z

Introduction to bus-based cache coherence in real machines

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	Most parallel software in the commercial market relies on the shared-memory		Most parallel software in the commercial market relies on the shared-memory
	programming model in which all processors access the same physical address space. The most common multiprocessors today use [http://en.wikipedia.org/wiki/Symmetric_multiprocessing SMP] architecture which use a common bus as the interconnect. In the case of multicore processors ("chip multiprocessors," or CMP) the [http://en.wikipedia.org/wiki/Symmetric_multiprocessing SMP] architecture applies to the cores treating them as separate processors. The key problem of shared-memory multiprocessors is providing a consistent view of memory with various cache hierarchies. This is called '''''[http://en.wikipedia.org/wiki/Cache_coherence cache coherence problem]'''''. It is critical to achieve correctness and performance-sensitive design point for supporting the shared-memory model. The cache coherence mechanisms not only govern communication in a shared-memory multiprocessor, but also typically determine how the memory system transfers data between processors, caches, and memory.		programming model in which all processors access the same physical address space. The most common multiprocessors today use [http://en.wikipedia.org/wiki/Symmetric_multiprocessing SMP] architecture which use a common bus as the interconnect. In the case of multicore processors ("chip multiprocessors," or [http://en.wikipedia.org/wiki/Multi-core_(computing) CMP]) the [http://en.wikipedia.org/wiki/Symmetric_multiprocessing SMP] architecture applies to the cores treating them as separate processors. The key problem of shared-memory multiprocessors is providing a consistent view of memory with various cache hierarchies. This is called '''''[http://en.wikipedia.org/wiki/Cache_coherence cache coherence problem]'''''. It is critical to achieve correctness and performance-sensitive design point for supporting the shared-memory model. The cache coherence mechanisms not only govern communication in a shared-memory multiprocessor, but also typically determine how the memory system transfers data between processors, caches, and memory.

	[[Image:Busbased SMP.jpg\|frame\|center\|<b>Figure 1:</b> Typical Bus-Based Processor Model]]		[[Image:Busbased SMP.jpg\|frame\|center\|<b>Figure 1:</b> Typical Bus-Based Processor Model]]

Chhildeb: /* Definitions */

2011-04-17T23:44:58Z

Definitions

← Older revision		Revision as of 23:44, 17 April 2011
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	=Definitions=		=Definitions=
	* Cache coherence - refers to the consistency of data stored in local caches of a shared resource.		* '''Cache coherence''' - refers to the consistency of data stored in local caches of a shared resource.
	* Chip multiprocessor (CMP) – a microprocess that has multiple cores integrated onto a single integrated circuit die.		* '''Chip multiprocessor (CMP)''' – a microprocess that has multiple cores integrated onto a single integrated circuit die.
	* Coherency protocol - a protocol which maintains the consistency between all the caches in a system of distributed shared memory.		* '''Coherency protocol''' - a protocol which maintains the consistency between all the caches in a system of distributed shared memory.
	* Front-side bus (FSB) - the bus that carries data between the CPU and the northbridge.		* '''Front-side bus (FSB)''' - the bus that carries data between the CPU and the northbridge.
	* Intel QuickPath Interconnect - a point-to-point processor interconnect developed by Intel which replaces the Front Side Bus (FSB) in Xeon, Itanium, and certain desktop platforms.		* '''Intel QuickPath Interconnect''' - a point-to-point processor interconnect developed by Intel which replaces the Front Side Bus (FSB) in Xeon, Itanium, and certain desktop platforms.
	* Spatial locality - if a particular memory location is referenced at a particular time, then it is likely that nearby memory locations will be referenced in the near future.		* '''Spatial locality''' - if a particular memory location is referenced at a particular time, then it is likely that nearby memory locations will be referenced in the near future.
	* Symmetric multiprocessing (SMP) - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.		* '''Symmetric multiprocessing (SMP)''' - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.
	* Temporal locality - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.		* '''Temporal locality''' - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.

	=References=		=References=

Chhildeb: /* Definitions */

2011-04-17T23:43:53Z

Definitions

← Older revision		Revision as of 23:43, 17 April 2011
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	=Definitions=		=Definitions=
	Cache coherence - refers to the consistency of data stored in local caches of a shared resource.		* Cache coherence - refers to the consistency of data stored in local caches of a shared resource.
	Chip multiprocessor (CMP) – a microprocess that has multiple cores integrated onto a single integrated circuit die.		* Chip multiprocessor (CMP) – a microprocess that has multiple cores integrated onto a single integrated circuit die.
	Coherency protocol - a protocol which maintains the consistency between all the caches in a system of distributed shared memory.		* Coherency protocol - a protocol which maintains the consistency between all the caches in a system of distributed shared memory.
	Front-side bus (FSB) - the bus that carries data between the CPU and the northbridge.		* Front-side bus (FSB) - the bus that carries data between the CPU and the northbridge.
	Intel QuickPath Interconnect - a point-to-point processor interconnect developed by Intel which replaces the Front Side Bus (FSB) in Xeon, Itanium, and certain desktop platforms.		* Intel QuickPath Interconnect - a point-to-point processor interconnect developed by Intel which replaces the Front Side Bus (FSB) in Xeon, Itanium, and certain desktop platforms.
	Spatial locality - if a particular memory location is referenced at a particular time, then it is likely that nearby memory locations will be referenced in the near future.		* Spatial locality - if a particular memory location is referenced at a particular time, then it is likely that nearby memory locations will be referenced in the near future.
	Symmetric multiprocessing (SMP) - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.		* Symmetric multiprocessing (SMP) - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.
	Temporal locality - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.		* Temporal locality - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.


	=References=		=References=

Chhildeb at 23:42, 17 April 2011

2011-04-17T23:42:30Z

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	The hybrid-Jetty is simply a combinations of and include and exclude-Jetty. Both types of Jetty are present and when a lookup occurs, both Jettys are checked to determine if a cache lookup is necessary.		The hybrid-Jetty is simply a combinations of and include and exclude-Jetty. Both types of Jetty are present and when a lookup occurs, both Jettys are checked to determine if a cache lookup is necessary.

			=Definitions=
			Cache coherence - refers to the consistency of data stored in local caches of a shared resource.
			Chip multiprocessor (CMP) – a microprocess that has multiple cores integrated onto a single integrated circuit die.
			Coherency protocol - a protocol which maintains the consistency between all the caches in a system of distributed shared memory.
			Front-side bus (FSB) - the bus that carries data between the CPU and the northbridge.
			Intel QuickPath Interconnect - a point-to-point processor interconnect developed by Intel which replaces the Front Side Bus (FSB) in Xeon, Itanium, and certain desktop platforms.
			Spatial locality - if a particular memory location is referenced at a particular time, then it is likely that nearby memory locations will be referenced in the near future.
			Symmetric multiprocessing (SMP) - a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance.
			Temporal locality - if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.


	=References=		=References=

Chhildeb: /* Optimization techniques on MOESI when implemented on AMD Phenom processors */

2011-04-17T23:41:08Z

Optimization techniques on MOESI when implemented on AMD Phenom processors

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	When the producer thread , writes a new entry, it allocates cache-lines in the '''M''' state. Eventually, these M-marked cache lines will start to fill the L3 cache. When the consumer reads the cache line, the [http://en.wikipedia.org/wiki/MOESI_protocol MOESI] protocol changes the state of the cache line to the '''O''' state in the L3 cache and pulls down a '''shared (S)''' copy for its own use. Now, the producer thread circles the ring buffer to arrive back to the same cache line it had previously written. However, when the producer attempts to write new data to the owned (marked '''‘O’''') cache line, it finds that it cannot, since a cache line in the '''O''' state by the previous consumer read does not have sufficient permission for a write request (in the [http://en.wikipedia.org/wiki/MOESI_protocol MOESI]). To maintain coherence, the memory controller must initiate probes in the other caches (to handle any other S copies that may exist). This will slow down the process.		When the producer thread , writes a new entry, it allocates cache-lines in the '''M''' state. Eventually, these M-marked cache lines will start to fill the L3 cache. When the consumer reads the cache line, the [http://en.wikipedia.org/wiki/MOESI_protocol MOESI] protocol changes the state of the cache line to the '''O''' state in the L3 cache and pulls down a '''shared (S)''' copy for its own use. Now, the producer thread circles the ring buffer to arrive back to the same cache line it had previously written. However, when the producer attempts to write new data to the owned (marked '''‘O’''') cache line, it finds that it cannot, since a cache line in the '''O''' state by the previous consumer read does not have sufficient permission for a write request (in the [http://en.wikipedia.org/wiki/MOESI_protocol MOESI]). To maintain coherence, the memory controller must initiate probes in the other caches (to handle any other S copies that may exist). This will slow down the process.

	Thus, it is preferable to keep the cache line in the '''M''' state in the L3 cache. In such a situation, when the producer comes back around the ring buffer, it finds the previously written cache line still in the'''M''' state, to which it is safe to write without coherence concerns. Thus better performance can be achieved by such optimization techniques to standard protocols when implemented in real machines.		Thus, it is preferable to keep the cache line in the '''M''' state in the L3 cache. In such a situation, when the producer comes back around the ring buffer, it finds the previously written cache line still in the '''M''' state, to which it is safe to write without coherence concerns. Thus better performance can be achieved by such optimization techniques to standard protocols when implemented in real machines.

	You can find more information on how this is implemented and various other ways of optimizations in this manual [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/40546.pdf Software Optimization guide for AMD 10h Processors].		You can find more information on how this is implemented and various other ways of optimizations in this manual [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/40546.pdf Software Optimization guide for AMD 10h Processors].