CSC/ECE 506 Spring 2011/ch7 jp - Revision history

Admin: /* Disadvantages of shared memory system */

2011-05-02T02:46:38Z

Disadvantages of shared memory system

← Older revision		Revision as of 02:46, 2 May 2011
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	==Disadvantages of shared memory system==		==Disadvantages of shared memory system==

	* Cost of providing shared memory grows ~~super linearly~~ with number of processors compared to message passing model which grows linearly.		* Cost of providing shared memory grows superlinearly with number of processors compared to message passing model which grows linearly.

	==Hardware Support ==		==Hardware Support ==

Pmpatel: /* Introduction */

2011-03-22T02:42:41Z

Introduction

← Older revision		Revision as of 02:42, 22 March 2011
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	=Introduction=		=Introduction=

	Shared memory architecture is one of the two major classes of large computer systems. In a shared memory architecture, physical memory from all the processors is mapped into a single memory map. All the processors can potentially access to all the memory on the system, although access time could be different (eg NUMA). Different threads or processes can communicate by reading/writing to shared memory.		Shared memory architecture is one of the two major classes of large computer systems architecture. In a shared memory architecture, physical memory from all the processors is mapped into a single memory map. All the processors can potentially access to all the memory on the system, although access time could be different (eg NUMA). Different threads or processes can communicate by reading/writing to shared memory.

	==Advantages of shared memory system==		==Advantages of shared memory system==

Pmpatel at 02:41, 22 March 2011

2011-03-22T02:41:59Z

← Older revision		Revision as of 02:41, 22 March 2011
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	=Introduction=		=Introduction=

	Shared memory architecture is one of the two major classes of large computer systems. In a shared memory architecture, physical memory from all the processors is mapped into a single memory map. All the processors can potentially access to all the memory on the system, although access time could be different (eg NUMA).		Shared memory architecture is one of the two major classes of large computer systems. In a shared memory architecture, physical memory from all the processors is mapped into a single memory map. All the processors can potentially access to all the memory on the system, although access time could be different (eg NUMA). Different threads or processes can communicate by reading/writing to shared memory.

	==Advantages of shared memory system==		==Advantages of shared memory system==

Pmpatel: /* Peterson's Algorithm */

2011-03-22T02:34:31Z

Peterson's Algorithm

← Older revision		Revision as of 02:34, 22 March 2011
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	interested[process] = 0;		interested[process] = 0;
	}		}

	The algorithm uses two variables as seen above, interested and turn. If a flag value for interested is set to 1, it indicates the process wants to enter the critical section. The variable turn is a placeholder for the process whose turn will be next allowed to enter the critical section. As seen above, Process1 has been given priority over P0.		The algorithm uses two variables as seen above, interested and turn. If a flag value for interested is set to 1, it indicates the process wants to enter the critical section. The variable turn is a placeholder for the process whose turn will be next allowed to enter the critical section. As seen above, Process1 has been given priority over P0.

Pmpatel: /* Cache Coherence Problem */

2011-03-22T02:31:09Z

Cache Coherence Problem

← Older revision		Revision as of 02:31, 22 March 2011
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	[[Image:sharedmem.jpg\|thumbnail\|right\|~~700px~~\|Shared Memory system with dedicated Cache for each processor<sup><span id="3body">[[#4foot\|[4]]]</span></sup>]]		[[Image:sharedmem.jpg\|thumbnail\|right\|600px\|Shared Memory system with dedicated Cache for each processor<sup><span id="3body">[[#4foot\|[4]]]</span></sup>]]

	In a system with single processor (single core), maintaining cache coherency is simple and easy but in a multiprocessor system, it is not as simple. Data can be present in any processors cache and protocol needs to ensure that the data is same in all caches. If it cannot ensure that all the caches are same, then it needs to flag a cache line indicating that it is not updated.		In a system with single processor (single core), maintaining cache coherency is simple and easy but in a multiprocessor system, it is not as simple. Data can be present in any processors cache and protocol needs to ensure that the data is same in all caches. If it cannot ensure that all the caches are same, then it needs to flag a cache line indicating that it is not updated.

Pmpatel: /* Cache Coherence Problem */

2011-03-22T02:30:48Z

Cache Coherence Problem

← Older revision		Revision as of 02:30, 22 March 2011
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	[[Image:sharedmem.jpg\|thumbnail\|right\|~~500px~~\|Shared Memory<sup><span id="3body">[[#4foot\|[4]]]</span></sup>]]		[[Image:sharedmem.jpg\|thumbnail\|right\|700px\|Shared Memory system with dedicated Cache for each processor<sup><span id="3body">[[#4foot\|[4]]]</span></sup>]]

	In a system with single processor (single core), maintaining cache coherency is simple and easy but in a multiprocessor system, it is not as simple. Data can be present in any processors cache and protocol needs to ensure that the data is same in all caches. If it cannot ensure that all the caches are same, then it needs to flag a cache line indicating that it is not updated.		In a system with single processor (single core), maintaining cache coherency is simple and easy but in a multiprocessor system, it is not as simple. Data can be present in any processors cache and protocol needs to ensure that the data is same in all caches. If it cannot ensure that all the caches are same, then it needs to flag a cache line indicating that it is not updated.

Pmpatel: /* Introduction */

2011-03-22T02:29:11Z

Introduction

← Older revision		Revision as of 02:29, 22 March 2011
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	=Introduction=		=Introduction=

	~~<copy introduction to~~ shared memory architecture ~~form previous chapters >~~		Shared memory architecture is one of the two major classes of large computer systems. In a shared memory architecture, physical memory from all the processors is mapped into a single memory map. All the processors can potentially access to all the memory on the system, although access time could be different (eg NUMA).

	==Advantages of shared memory system==		==Advantages of shared memory system==
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	# Cache Coherence protocol		# Cache Coherence protocol
	# Memory consistency model		# Memory consistency model
	# Hardware Synchronization		# Hardware Synchronization


	=Cache Coherence Problem=		=Cache Coherence Problem=

Avylen at 02:26, 22 March 2011

2011-03-22T02:26:22Z

← Older revision		Revision as of 02:26, 22 March 2011
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	Maintaining program order is very important for memory consistency but it comes with performance degradation. Various memory consistency models trades off performance to make programming easy.		Maintaining program order is very important for memory consistency but it comes with performance degradation. Various memory consistency models trades off performance to make programming easy.

	~~=Hardware Synchronization=~~

	=Peterson's Algorithm=		=Peterson's Algorithm=

Avylen: /* Cache Coherence Problem */

2011-03-22T02:21:22Z

Cache Coherence Problem

← Older revision		Revision as of 02:21, 22 March 2011
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	[[Image:sharedmem.jpg\|thumbnail\|~~left~~\|500px\|Shared Memory<sup><span id="3body">[[#4foot\|[4]]]</span></sup>]]		[[Image:sharedmem.jpg\|thumbnail\|right\|500px\|Shared Memory<sup><span id="3body">[[#4foot\|[4]]]</span></sup>]]

	In a system with single processor (single core), maintaining cache coherency is simple and easy but in a multiprocessor system, it is not as simple. Data can be present in any processors cache and protocol needs to ensure that the data is same in all caches. If it cannot ensure that all the caches are same, then it needs to flag a cache line indicating that it is not updated.		In a system with single processor (single core), maintaining cache coherency is simple and easy but in a multiprocessor system, it is not as simple. Data can be present in any processors cache and protocol needs to ensure that the data is same in all caches. If it cannot ensure that all the caches are same, then it needs to flag a cache line indicating that it is not updated.

Avylen: /* Cache Coherence Problem */

2011-03-22T02:21:15Z

Cache Coherence Problem

← Older revision		Revision as of 02:21, 22 March 2011
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	[[Image:sharedmem.jpg\|thumbnail\|~~center~~\|500px\|Shared Memory<sup><span id="3body">[[#4foot\|[4]]]</span></sup>]]		[[Image:sharedmem.jpg\|thumbnail\|left\|500px\|Shared Memory<sup><span id="3body">[[#4foot\|[4]]]</span></sup>]]

	In a system with single processor (single core), maintaining cache coherency is simple and easy but in a multiprocessor system, it is not as simple. Data can be present in any processors cache and protocol needs to ensure that the data is same in all caches. If it cannot ensure that all the caches are same, then it needs to flag a cache line indicating that it is not updated.		In a system with single processor (single core), maintaining cache coherency is simple and easy but in a multiprocessor system, it is not as simple. Data can be present in any processors cache and protocol needs to ensure that the data is same in all caches. If it cannot ensure that all the caches are same, then it needs to flag a cache line indicating that it is not updated.