CSC/ECE 506 Spring 2011/ch6a jp - Revision history

Avylen: /* Cache Hierarchy */

2011-02-28T00:20:40Z

Cache Hierarchy

← Older revision		Revision as of 00:20, 28 February 2011
Line 7:		Line 7:
	There can be multiple levels of caches, each cache subsequently away from the core and larger in size. L1 is closest to the CPU and as a result, fastest to excess. Next to L1 is L2 cache and then L3. L1 cache is divided into instruction cache and data cache. This is better than having a combined larger cache as instruction cache being read-only is easy to implement while data cache is read-write.<br>		There can be multiple levels of caches, each cache subsequently away from the core and larger in size. L1 is closest to the CPU and as a result, fastest to excess. Next to L1 is L2 cache and then L3. L1 cache is divided into instruction cache and data cache. This is better than having a combined larger cache as instruction cache being read-only is easy to implement while data cache is read-write.<br>

	[[Image:Uniprocessor_memory_hierarchy.jpg\|thumbnail\|~~300px~~\|Uniprocessor memory hierarchy<sup><span id="2body">[[#2foot\|[2]]]</span></sup>]]		[[Image:Uniprocessor_memory_hierarchy.jpg\|thumbnail\|200px\|Uniprocessor memory hierarchy<sup><span id="2body">[[#2foot\|[2]]]</span></sup>]]
	[[Image:Dualcore_memory_hierarchy.jpg\|thumbnail\|~~300px~~\|Dualcore memory hierarchy<sup><span id="3body">[[#3foot\|[3]]]</span></sup>]]		[[Image:Dualcore_memory_hierarchy.jpg\|thumbnail\|200px\|Dualcore memory hierarchy<sup><span id="3body">[[#3foot\|[3]]]</span></sup>]]

	{\| border='1' class="wikitable" style="text-align:center"		{\| border='1' class="wikitable" style="text-align:center"

Avylen: /* Cache Hierarchy */

2011-02-28T00:20:13Z

Cache Hierarchy

← Older revision		Revision as of 00:20, 28 February 2011
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	=Cache Hierarchy=		=Cache Hierarchy=
	[[Image: memchart.jpg\|thumbnail\|right\|Memory Hierarchy<sup><span id="9body">[[#9foot\|[9]]]</span></sup>]]		[[Image: memchart.jpg\|thumbnail\|300px\|right\|Memory Hierarchy<sup><span id="9body">[[#9foot\|[9]]]</span></sup>]]
	In a simple computer model, processor reads data and instructions from the memory and operates on the data. Operating frequency of CPU increased faster than the speed of memory and memory interconnects. For example, cores in Intel first generation i7 processors run at 3.2 GHz frequency, while the memory only runs at 1.3GHz frequency. Also, multi-core architecture started putting more demand on memory bandwidth. This increases the latency in memory access and CPU will have to be idle for most of the time. Due to this, memory became a bottle neck in performance.		In a simple computer model, processor reads data and instructions from the memory and operates on the data. Operating frequency of CPU increased faster than the speed of memory and memory interconnects. For example, cores in Intel first generation i7 processors run at 3.2 GHz frequency, while the memory only runs at 1.3GHz frequency. Also, multi-core architecture started putting more demand on memory bandwidth. This increases the latency in memory access and CPU will have to be idle for most of the time. Due to this, memory became a bottle neck in performance.

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	There can be multiple levels of caches, each cache subsequently away from the core and larger in size. L1 is closest to the CPU and as a result, fastest to excess. Next to L1 is L2 cache and then L3. L1 cache is divided into instruction cache and data cache. This is better than having a combined larger cache as instruction cache being read-only is easy to implement while data cache is read-write.<br>		There can be multiple levels of caches, each cache subsequently away from the core and larger in size. L1 is closest to the CPU and as a result, fastest to excess. Next to L1 is L2 cache and then L3. L1 cache is divided into instruction cache and data cache. This is better than having a combined larger cache as instruction cache being read-only is easy to implement while data cache is read-write.<br>

	[[Image:Uniprocessor_memory_hierarchy.jpg\|thumbnail\|Uniprocessor memory hierarchy<sup><span id="2body">[[#2foot\|[2]]]</span></sup>]]		[[Image:Uniprocessor_memory_hierarchy.jpg\|thumbnail\|300px\|Uniprocessor memory hierarchy<sup><span id="2body">[[#2foot\|[2]]]</span></sup>]]
	[[Image:Dualcore_memory_hierarchy.jpg\|thumbnail\|Dualcore memory hierarchy<sup><span id="3body">[[#3foot\|[3]]]</span></sup>]]		[[Image:Dualcore_memory_hierarchy.jpg\|thumbnail\|300px\|Dualcore memory hierarchy<sup><span id="3body">[[#3foot\|[3]]]</span></sup>]]

	{\| border='1' class="wikitable" style="text-align:center"		{\| border='1' class="wikitable" style="text-align:center"

Avylen: /* Cache Write Policies */

2011-02-27T18:19:20Z

Cache Write Policies

← Older revision		Revision as of 18:19, 27 February 2011
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	==Write hit policies==		==Write hit policies==
	[[Image:Cache_policy_comparison.jpg\|thumbnail\|~~300px~~\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]		[[Image:Cache_policy_comparison.jpg\|thumbnail\|600px\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]
	*Write-through: Also known as store-through, this policy will write to main memory whenever a write is performed to cache.		*Write-through: Also known as store-through, this policy will write to main memory whenever a write is performed to cache.
	**Advantages:		**Advantages:

Avylen: /* Cache Write Policies */

2011-02-27T18:19:10Z

Cache Write Policies

← Older revision		Revision as of 18:19, 27 February 2011
Line 51:		Line 51:

	==Write hit policies==		==Write hit policies==
			[[Image:Cache_policy_comparison.jpg\|thumbnail\|300px\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]
	*Write-through: Also known as store-through, this policy will write to main memory whenever a write is performed to cache.		*Write-through: Also known as store-through, this policy will write to main memory whenever a write is performed to cache.
	**Advantages:		**Advantages:
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	==Combination Policies==		==Combination Policies==
	~~[[Image:Cache_policy_comparison.jpg\|thumbnail\|300px\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]~~
	* Write-validate: It is a combination of no-fetch-on-write and write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. The policy allows partial lines to be written to the cache on a miss. It provides for better performance as well as works with machines that have various line sizes and does not add instruction execution overhead to the program being run. Write-validate requires that the lower level system memory can support writes of partial lines.		* Write-validate: It is a combination of no-fetch-on-write and write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. The policy allows partial lines to be written to the cache on a miss. It provides for better performance as well as works with machines that have various line sizes and does not add instruction execution overhead to the program being run. Write-validate requires that the lower level system memory can support writes of partial lines.
	* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.		* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.

Avylen: /* Combination Policies */

2011-02-27T18:18:43Z

Combination Policies

← Older revision		Revision as of 18:18, 27 February 2011
Line 76:		Line 76:

	==Combination Policies==		==Combination Policies==
			[[Image:Cache_policy_comparison.jpg\|thumbnail\|300px\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]
	* Write-validate: It is a combination of no-fetch-on-write and write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. The policy allows partial lines to be written to the cache on a miss. It provides for better performance as well as works with machines that have various line sizes and does not add instruction execution overhead to the program being run. Write-validate requires that the lower level system memory can support writes of partial lines.		* Write-validate: It is a combination of no-fetch-on-write and write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. The policy allows partial lines to be written to the cache on a miss. It provides for better performance as well as works with machines that have various line sizes and does not add instruction execution overhead to the program being run. Write-validate requires that the lower level system memory can support writes of partial lines.
	* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.		* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.
	* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.		* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.
	~~[[Image:Cache_policy_comparison.jpg\|thumbnail\|300px\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]~~

	=Prefetching=		=Prefetching=

Avylen: /* Combination Policies */

2011-02-27T18:18:30Z

Combination Policies

← Older revision		Revision as of 18:18, 27 February 2011
Line 80:		Line 80:
	* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.		* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.
	* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.		* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.
	[[Image:Cache_policy_comparison.jpg\|thumbnail\|~~150p~~\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]		[[Image:Cache_policy_comparison.jpg\|thumbnail\|300px\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]

	=Prefetching=		=Prefetching=

Avylen: /* Combination Policies */

2011-02-27T18:18:21Z

Combination Policies

← Older revision		Revision as of 18:18, 27 February 2011
Line 76:		Line 76:

	==Combination Policies==		==Combination Policies==
	~~[[Image:Cache_policy_comparison.jpg\|thumbnail\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]~~
	* Write-validate: It is a combination of no-fetch-on-write and write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. The policy allows partial lines to be written to the cache on a miss. It provides for better performance as well as works with machines that have various line sizes and does not add instruction execution overhead to the program being run. Write-validate requires that the lower level system memory can support writes of partial lines.		* Write-validate: It is a combination of no-fetch-on-write and write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. The policy allows partial lines to be written to the cache on a miss. It provides for better performance as well as works with machines that have various line sizes and does not add instruction execution overhead to the program being run. Write-validate requires that the lower level system memory can support writes of partial lines.
	* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.		* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.
	* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.		* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.
			[[Image:Cache_policy_comparison.jpg\|thumbnail\|150p\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]

	=Prefetching=		=Prefetching=

Avylen: /* Combination Policies */

2011-02-27T18:17:03Z

Combination Policies

← Older revision		Revision as of 18:17, 27 February 2011
Line 76:		Line 76:

	==Combination Policies==		==Combination Policies==
			[[Image:Cache_policy_comparison.jpg\|thumbnail\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]
	* Write-validate: It is a combination of no-fetch-on-write and write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. The policy allows partial lines to be written to the cache on a miss. It provides for better performance as well as works with machines that have various line sizes and does not add instruction execution overhead to the program being run. Write-validate requires that the lower level system memory can support writes of partial lines.		* Write-validate: It is a combination of no-fetch-on-write and write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. The policy allows partial lines to be written to the cache on a miss. It provides for better performance as well as works with machines that have various line sizes and does not add instruction execution overhead to the program being run. Write-validate requires that the lower level system memory can support writes of partial lines.
	* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.		* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.
	* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.		* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.
	~~[[Image:Cache_policy_comparison.jpg\|thumbnail\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]~~

	=Prefetching=		=Prefetching=

Avylen: /* Combination Policies */

2011-02-27T18:16:47Z

Combination Policies

← Older revision		Revision as of 18:16, 27 February 2011
Line 79:		Line 79:
	* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.		* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.
	* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.		* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.
	[[Image:Cache_policy_comparison.jpg\|~~center~~\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]		[[Image:Cache_policy_comparison.jpg\|thumbnail\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]

	=Prefetching=		=Prefetching=

Avylen: /* Combination Policies */

2011-02-27T18:16:24Z

Combination Policies

← Older revision		Revision as of 18:16, 27 February 2011
Line 79:		Line 79:
	* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.		* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.
	* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.		* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.

	[[Image:Cache_policy_comparison.jpg\|center\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]		[[Image:Cache_policy_comparison.jpg\|center\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]

← Older revision		Revision as of 18:16, 27 February 2011
Line 79:		Line 79:
	* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.		* Write-invalidate: This policy is a combination of write-before-hit, no-fetch-on-write, and no-write-allocate<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy invalidates lines when there is a miss.
	* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.		* Write-around: Combination of no-fetch-on-write, no-write-allocate, and no-write-before-hit<sup><span id="4body">[[#4foot\|[4]]]</span></sup>. This policy uses a non-blocking write scheme to write to cache. It writes data to the next lower cache without modifying the data of the cache line.

	[[Image:Cache_policy_comparison.jpg\|center\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]		[[Image:Cache_policy_comparison.jpg\|center\|Cache policy comparison<sup><span id="5body">[[#5foot\|[5]]]</span></sup>]]