CSC/ECE 506 Spring 2011/ch3 ab - Revision history

Akrepask at 21:05, 21 February 2011

2011-02-21T21:05:09Z

Akrepask at 06:24, 14 February 2011

2011-02-14T06:24:49Z

← Older revision		Revision as of 06:24, 14 February 2011
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	===Cell Broadband Engine===		===Cell Broadband Engine===
	Cell Broadband Engine, also referred to as Cell or Cell BE, is an IBM architecture whose first major application was in Sony’s PlayStation 3. Cell has streamlined coprocessing elements which is great for fast multimedia and vector processing applications. [[#References\|<sup>[20]</sup>]]		Cell Broadband Engine Architecture, also referred to as Cell or Cell BE, is an IBM architecture whose first major application was in Sony’s PlayStation 3. Cell has streamlined coprocessing elements which is great for fast multimedia and vector processing applications. [[#References\|<sup>[20]</sup>]]

	This architecture is interesting because it uses a shared memory model in which the LOADs and STORES use a “weakly consistent” storage model. Meaning that, the sequence in which any of the following orders are executed in may be different from each other: [[#References\|<sup>[19]</sup>]]

	*The order of any processor element (PPE or SPE) performing storage access		This architecture is interesting because it uses a shared memory model in which the LOADs and STOREs use a “weakly consistent” storage model. Meaning that, the sequence in which any of the following orders are executed may be different from each other: [[#References\|<sup>[19]</sup>]]
	* The order in which the accesses are performed with respect to another
	processor element		* The order of any processor element (PPE or SPE) performing storage access
	*The order in which the accesses are performed in main storage		* The order in which the accesses are performed with respect to another processor element
			* The order in which the accesses are performed in main storage

	It is important that the accesses to the shared memory happen in the correct program order or information could be lost or corrupted. In order to ensure that this doesn’t happen the following memory barrier instructions are used:		It is important that the accesses to the shared memory happen in the correct program order or information could be lost or corrupted. In order to ensure that this doesn’t happen the following memory barrier instructions are used:

	====Fence====		====Fence====
	After all previous issued commands within the same “tag group” have been performed the fence instruction can be issued. If there is a command that is issued after the fence command, it might be executed before the fence command.		After all previous issued commands within the same “tag group” have been performed the fence instruction can be issued. If there is a command that is issued after the fence command, it might be executed before the fence command. [[#References\|<sup>[19]</sup>]]

	====Barrier====		====Barrier====
	After all previous issued commands have been performed, the barrier command and all of the instructions after the barrier command can be executed.		After all previous issued commands have been performed, the barrier command and all of the instructions after the barrier command can then be executed. [[#References\|<sup>[19]</sup>]]

	~~The diagram below demonstrates this behavior.~~

Akrepask at 06:15, 14 February 2011

2011-02-14T06:15:38Z

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+   {
 ==References==
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 <li>[http://www.google.com/url?sa=t&source=web&cd=6&ved=0CEQQFjAF&url=http%3A%2F%2Flinuxindore.com%2Fdownloads%2Fdownload%2Fdata-structures%2Flinux-kernel-arch&ei=jxZWTaGTNI34sAPWm-ScDA&usg=AFQjCNG9UOAz7rHfwUDfayhr50M87uNOYA&sig2=azvo4h85RkoNHcZUtNIkJw Linux Kernel Architecture Overveiw]</li>
 <li>[http://pg-server.csc.ncsu.edu/mediawiki/index.php/CSC/ECE_506_Spring_2010/ch_3_jb/Parallel_Programming_Model_Support Spring 2010 NC State ECE/CSC506 Chapter 3 wiki]</li>
 </ol>

Akrepask at 04:32, 14 February 2011

2011-02-14T04:32:33Z

← Older revision		Revision as of 04:32, 14 February 2011
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	*Intel TBB relies on generic programming, it performs better with custom iteration spaces or complex reduction operations. Also, it provides generic parallel patterns for parallel while-loops, data-flow pipeline models, parallel sorts and prefixes, so it's better in cases that go beyond loop-based parallelism.		*Intel TBB relies on generic programming, it performs better with custom iteration spaces or complex reduction operations. Also, it provides generic parallel patterns for parallel while-loops, data-flow pipeline models, parallel sorts and prefixes, so it's better in cases that go beyond loop-based parallelism.

	Below is a table that ~~illistrates~~ the differences [[#References\|<sup>[16]</sup>]]		Below is a table that illustrates the differences [[#References\|<sup>[16]</sup>]]
	{\| align="center cellpadding="4"		{\| align="center cellpadding="4"

Akrepask at 04:21, 14 February 2011

2011-02-14T04:21:54Z

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 *Intel TBB relies on generic programming, it performs better with custom iteration spaces or complex reduction operations. Also, it provides generic parallel patterns for parallel while-loops, data-flow pipeline models, parallel sorts and prefixes, so it's better in cases that go beyond loop-based parallelism.
 ==Synchronization Mechanisms==
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 <li>[http://developer.download.nvidia.com/compute/cuda/3_2_prod/toolkit/docs/CUDA_C_Programming_Guide.pdf CUDA Programming Guide]</li>
 <li>[http://www.google.com/url?sa=t&source=web&cd=6&ved=0CEQQFjAF&url=http%3A%2F%2Flinuxindore.com%2Fdownloads%2Fdownload%2Fdata-structures%2Flinux-kernel-arch&ei=jxZWTaGTNI34sAPWm-ScDA&usg=AFQjCNG9UOAz7rHfwUDfayhr50M87uNOYA&sig2=azvo4h85RkoNHcZUtNIkJw Linux Kernel Architecture Overveiw]</li>
 </ol>

Akrepask at 04:10, 14 February 2011

2011-02-14T04:10:53Z

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Akrepask: testing

2011-02-12T03:53:57Z

testing

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