CSC/ECE 506 Spring 2011/ch2a mc - Revision history

Admin: /* Platform Model */

2011-03-21T01:57:42Z

Platform Model

← Older revision		Revision as of 01:57, 21 March 2011
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	[[Image:OpenCL_Fig1.png\|frame\|center\|<b>Figure 1:</b> [[#Definitions\|OpenCL]] Platform Model [[#References\|<sup>[1]</sup>]]]]		[[Image:OpenCL_Fig1.png\|frame\|center\|<b>Figure 1:</b> [[#Definitions\|OpenCL]] Platform Model [[#References\|<sup>[1]</sup>]]]]

	As shown in Figure 1, the platform for running [[#Definitions\|OpenCL]] programs somewhat resembles a network of computer clusters. The similarity is quite significant, each Compute Device behaves like a cluster, which consists of computers (in the form of Compute Unit - CU), and each Compute Unit can contain multiple Processing ~~Element~~(PE), much like a computer can contain multiple [[#Definitions\|CPUs]].		As shown in Figure 1, the platform for running [[#Definitions\|OpenCL]] programs somewhat resembles a network of computer clusters. The similarity is quite significant, each Compute Device behaves like a cluster, which consists of computers (in the form of Compute Unit - CU), and each Compute Unit can contain multiple Processing Elements (PEs), much like a computer can contain multiple [[#Definitions\|CPUs]].

	===Execution Model===		===Execution Model===

Chhildeb: /* CUDA Programming */

2011-02-24T01:50:50Z

CUDA Programming

← Older revision		Revision as of 01:50, 24 February 2011
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	</pre>		</pre>

	The line 'square_array square_array <<< n_blocks, block_size >>> (a_d, N);' is where the main [[#Definitions\|CPU]] hands off the execution to the [[#Definitions\|GPU]. The amount of parallelism utilized in 'square_array' depends on the number of blocks and the block size, which is allocated by the programmer. [[#Definitions\|CUDA]] will handle the details of the parallel execution for the programmer.		The line 'square_array square_array <<< n_blocks, block_size >>> (a_d, N);' is where the main [[#Definitions\|CPU]] hands off the execution to the [[#Definitions\|GPU]]. The amount of parallelism utilized in 'square_array' depends on the number of blocks and the block size, which is allocated by the programmer. [[#Definitions\|CUDA]] will handle the details of the parallel execution for the programmer.

	=Definitions=		=Definitions=

Chhildeb: /* AMD Implementation */

2011-02-19T21:40:16Z

AMD Implementation

← Older revision		Revision as of 21:40, 19 February 2011
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	As can be seen from Table 1, [[#Definitions\|GPUs]] can have a wide range of parameters, which often lead to performance differences. The top-of-the-line model like Radeon HD 6970 is equipped with more cores (PE), wider memory bus bandwidth and faster clock rate. As a result, it is much faster than a low-end model with significantly reduced configurations.		As can be seen from Table 1, [[#Definitions\|GPUs]] can have a wide range of parameters, which often lead to performance differences. The top-of-the-line model like Radeon HD 6970 is equipped with more cores (PE), wider memory bus bandwidth and faster clock rate. As a result, it is much faster than a low-end model with significantly reduced configurations.

	According to specification published by [http://en.wikipedia.org/wiki/Amd AMD][[#References\|<sup>[3]</sup>]], [http://en.wikipedia.org/wiki/Radeon Radeon] HD [[#Definitions\|GPU]] organization has significant similarity with [[#Definitions\|OpenCL]] platform model described above. The similarity can be seen from the figure below, where the DPP ~~Array~~ is essentially a group of CUs, local data share is simply a local memory region (in OpenCL terminology),		According to specification published by [http://en.wikipedia.org/wiki/Amd AMD][[#References\|<sup>[3]</sup>]], [http://en.wikipedia.org/wiki/Radeon Radeon] HD [[#Definitions\|GPU]] organization has significant similarity with [[#Definitions\|OpenCL]] platform model described above. The similarity can be seen from the figure below, where the DPP array is essentially a group of CUs, local data share is simply a local memory region (in OpenCL terminology),

	[[Image:OpenCL_Fig3.png\|frame\|center\|<b>Figure 3:</b> [http://en.wikipedia.org/wiki/Amd AMD] [http://en.wikipedia.org/wiki/Radeon Radeon] HD 6900 Series Block Diagram]]		[[Image:OpenCL_Fig3.png\|frame\|center\|<b>Figure 3:</b> [http://en.wikipedia.org/wiki/Amd AMD] [http://en.wikipedia.org/wiki/Radeon Radeon] HD 6900 Series Block Diagram]]

Chhildeb: /* AMD Implementation */

2011-02-19T21:39:27Z

AMD Implementation

← Older revision		Revision as of 21:39, 19 February 2011
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	As can be seen from Table 1, [[#Definitions\|GPUs]] can have a wide range of parameters, which often lead to performance differences. The top-of-the-line model like Radeon HD 6970 is equipped with more cores (PE), wider memory bus bandwidth and faster clock rate. As a result, it is much faster than a low-end model with significantly reduced configurations.		As can be seen from Table 1, [[#Definitions\|GPUs]] can have a wide range of parameters, which often lead to performance differences. The top-of-the-line model like Radeon HD 6970 is equipped with more cores (PE), wider memory bus bandwidth and faster clock rate. As a result, it is much faster than a low-end model with significantly reduced configurations.

	According to specification published by [http://en.wikipedia.org/wiki/Amd AMD][[#References\|<sup>[3]</sup>]], [http://en.wikipedia.org/wiki/Radeon Radeon] HD [[#Definitions\|GPU]] organization has significant similarity with [[#Definitions\|OpenCL]] platform model described above. The similarity can be seen from the figure below.		According to specification published by [http://en.wikipedia.org/wiki/Amd AMD][[#References\|<sup>[3]</sup>]], [http://en.wikipedia.org/wiki/Radeon Radeon] HD [[#Definitions\|GPU]] organization has significant similarity with [[#Definitions\|OpenCL]] platform model described above. The similarity can be seen from the figure below, where the DPP Array is essentially a group of CUs, local data share is simply a local memory region (in OpenCL terminology),

	[[Image:OpenCL_Fig3.png\|frame\|center\|<b>Figure 3:</b> [http://en.wikipedia.org/wiki/Amd AMD] [http://en.wikipedia.org/wiki/Radeon Radeon] HD 6900 Series Block Diagram]]		[[Image:OpenCL_Fig3.png\|frame\|center\|<b>Figure 3:</b> [http://en.wikipedia.org/wiki/Amd AMD] [http://en.wikipedia.org/wiki/Radeon Radeon] HD 6900 Series Block Diagram]]

Chhildeb: /* Execution Model */

2011-02-19T21:37:03Z

Execution Model

← Older revision		Revision as of 21:37, 19 February 2011
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	[[Image:OpenCL_Fig2.png\|frame\|center\|<b>Figure 2:</b> Execution Model [[#References\|<sup>[1]</sup>]]]]		[[Image:OpenCL_Fig2.png\|frame\|center\|<b>Figure 2:</b> Execution Model [[#References\|<sup>[1]</sup>]]]]

	Figure 2 depicts the conceptual model of execution. There is a ''host program'' which executes on the host and manages the execution of multiple ''compute kernels''. Each compute kernel can execute in parallel on separate ''work-items''. ~~Work~~-items ~~close together~~ can then be grouped into a ''work-group''. This execution model closely matches the platform model described above, as each PE often executes one kernel, and one ~~workgroup~~ is often handled by one CU.		Figure 2 depicts the conceptual model of execution. There is a ''host program'' which executes on the host and manages the execution of multiple ''compute kernels''. Each compute kernel can execute in parallel on separate ''work-items''. Related work-items can then be grouped into a ''work-group''. This execution model closely matches the platform model described above, as each PE often executes one kernel, and one work-group is often handled by one CU. In this way, communication overhead is reduced, thus improving performance.

	===Memory Model===		===Memory Model===

Chhildeb: /* Platform Model */

2011-02-19T21:36:26Z

Platform Model

← Older revision		Revision as of 21:36, 19 February 2011
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	[[Image:OpenCL_Fig1.png\|frame\|center\|<b>Figure 1:</b> [[#Definitions\|OpenCL]] Platform Model [[#References\|<sup>[1]</sup>]]]]		[[Image:OpenCL_Fig1.png\|frame\|center\|<b>Figure 1:</b> [[#Definitions\|OpenCL]] Platform Model [[#References\|<sup>[1]</sup>]]]]

	As shown in Figure 1, the platform for running [[#Definitions\|OpenCL]] programs somewhat resembles a network of computer clusters. The ~~parallel~~ is ~~relatively close:~~ each ~~compute device~~ behaves like a cluster, which consists of computers (in the form of ~~compute unit~~ - CU), and each ~~compute unit~~ can contain multiple ~~processing elements~~ (PE), much like a computer can contain multiple [[#Definitions\|CPUs]].		As shown in Figure 1, the platform for running [[#Definitions\|OpenCL]] programs somewhat resembles a network of computer clusters. The similarity is quite significant, each Compute Device behaves like a cluster, which consists of computers (in the form of Compute Unit - CU), and each Compute Unit can contain multiple Processing Element(PE), much like a computer can contain multiple [[#Definitions\|CPUs]].

	===Execution Model===		===Execution Model===

Chhildeb: /* Definitions */

2011-02-19T19:52:14Z

Definitions

← Older revision		Revision as of 19:52, 19 February 2011
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	*<i>Graphics Processing Unit (GPU)</i> - a dedicated processor designed to reduce the CPU load when rendering a video display. Can also perform general purpose calculations, also known as a GPGPU.		*<i>Graphics Processing Unit (GPU)</i> - a dedicated processor designed to reduce the CPU load when rendering a video display. Can also perform general purpose calculations, also known as a GPGPU.

	*<i>OpenCL</i> - An open parallel computing architecture that is supported by a number of hardware vendors, including [http://en.wikipedia.org/wiki/Amd AMD], [http://en.wikipedia.org/wiki/Nvidia Nvidia], S3, and VIA.		*<i>OpenCL</i> - An open parallel computing architecture that is supported by a number of hardware vendors, including [http://en.wikipedia.org/wiki/Amd AMD], [http://en.wikipedia.org/wiki/Nvidia Nvidia], [http://en.wikipedia.org/wiki/S3_Graphics S3 Graphics], and [http://en.wikipedia.org/wiki/VIA_Technologies VIA Technologies].

	*<i>PhysX</i> - a proprietary physics computation engine develeped by Ageia. PhysX can run on a dedicated PhysX physics processing unit or a CUDA-enabled [http://en.wikipedia.org/wiki/Geforce GeForce] GPU.		*<i>PhysX</i> - a proprietary physics computation engine develeped by [http://en.wikipedia.org/wiki/Ageia Ageia]. [http://en.wikipedia.org/wiki/Physx PhysX] can run on a dedicated [http://en.wikipedia.org/wiki/Physx PhysX] physics processing unit or a CUDA-enabled [http://en.wikipedia.org/wiki/Geforce GeForce] GPU.

	*<i>Stream Processor (SP)</i> - a specialized processor that allows limited floating point calculations to be performed without the need to explicitly manage the communication or synchronization between stream processors.		*<i>Stream Processor (SP)</i> - a specialized processor that allows limited floating point calculations to be performed without the need to explicitly manage the communication or synchronization between stream processors.

Chhildeb: /* Sample Application */

2011-02-19T19:49:41Z

Sample Application

← Older revision		Revision as of 19:49, 19 February 2011
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	===Sample Application===		===Sample Application===
	OpenCL applications are mainly implemented in C; a C++ wrapper built on top of C is also available. According to the [[#Definitions\|OpenCL]] 1.1 specification, the [[#Definitions\|OpenCL]] C language is based on ISO C99, with extensions designed for parallel computing[[#References\|<sup>[1]</sup>]]. The following is sample application to compute a Fast Fourier Transformation (FFT)[[#References\|<sup>[5]</sup>]].		[[#Definitions\|OpenCL]] applications are mainly implemented in C; a C++ wrapper built on top of C is also available. According to the [[#Definitions\|OpenCL]] 1.1 specification, the [[#Definitions\|OpenCL]] C language is based on ISO C99, with extensions designed for parallel computing[[#References\|<sup>[1]</sup>]]. The following is sample application to compute a Fast Fourier Transformation (FFT)[[#References\|<sup>[5]</sup>]].

	<pre>		<pre>

Chhildeb: /* Memory Model */

2011-02-19T19:48:23Z

Memory Model

← Older revision		Revision as of 19:48, 19 February 2011
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	===Memory Model===		===Memory Model===

	The memory model of [[#Definitions\|OpenCL]] reflects the design of the ~~Platform Model~~ and ~~Execution Model~~. Specifically, there are four levels of memory, as shown in the table below.		The memory model of [[#Definitions\|OpenCL]] reflects the design of the platform model and execution model. Specifically, there are four levels of memory, as shown in the table below.

	{\| border="1" align="center" style="text-align:center;"		{\| border="1" align="center" style="text-align:center;"

Chhildeb: /* Platform Model */

2011-02-19T19:48:00Z

Platform Model

← Older revision		Revision as of 19:48, 19 February 2011
Line 12:		Line 12:
	[[Image:OpenCL_Fig1.png\|frame\|center\|<b>Figure 1:</b> [[#Definitions\|OpenCL]] Platform Model [[#References\|<sup>[1]</sup>]]]]		[[Image:OpenCL_Fig1.png\|frame\|center\|<b>Figure 1:</b> [[#Definitions\|OpenCL]] Platform Model [[#References\|<sup>[1]</sup>]]]]

	As shown in Figure 1, the platform for running [[#Definitions\|OpenCL]] programs somewhat resembles a network of computer clusters. The parallel is relatively close: each ~~Compute Device~~ behaves like a cluster, which consists of computers (in the form of ~~Compute Unit~~ - CU), and each ~~Compute Unit~~ can contain multiple ~~Processing Element~~(PE), much like a computer can contain multiple [[#Definitions\|CPUs]].		As shown in Figure 1, the platform for running [[#Definitions\|OpenCL]] programs somewhat resembles a network of computer clusters. The parallel is relatively close: each compute device behaves like a cluster, which consists of computers (in the form of compute unit - CU), and each compute unit can contain multiple processing elements (PE), much like a computer can contain multiple [[#Definitions\|CPUs]].

	===Execution Model===		===Execution Model===

← Older revision		Revision as of 21:40, 19 February 2011
Line 182:		Line 182:
	As can be seen from Table 1, [[#Definitions\|GPUs]] can have a wide range of parameters, which often lead to performance differences. The top-of-the-line model like Radeon HD 6970 is equipped with more cores (PE), wider memory bus bandwidth and faster clock rate. As a result, it is much faster than a low-end model with significantly reduced configurations.		As can be seen from Table 1, [[#Definitions\|GPUs]] can have a wide range of parameters, which often lead to performance differences. The top-of-the-line model like Radeon HD 6970 is equipped with more cores (PE), wider memory bus bandwidth and faster clock rate. As a result, it is much faster than a low-end model with significantly reduced configurations.

	According to specification published by [http://en.wikipedia.org/wiki/Amd AMD][[#References\|<sup>[3]</sup>]], [http://en.wikipedia.org/wiki/Radeon Radeon] HD [[#Definitions\|GPU]] organization has significant similarity with [[#Definitions\|OpenCL]] platform model described above. The similarity can be seen from the figure below, where the DPP ~~Array~~ is essentially a group of CUs, local data share is simply a local memory region (in OpenCL terminology),		According to specification published by [http://en.wikipedia.org/wiki/Amd AMD][[#References\|<sup>[3]</sup>]], [http://en.wikipedia.org/wiki/Radeon Radeon] HD [[#Definitions\|GPU]] organization has significant similarity with [[#Definitions\|OpenCL]] platform model described above. The similarity can be seen from the figure below, where the DPP array is essentially a group of CUs, local data share is simply a local memory region (in OpenCL terminology),

	[[Image:OpenCL_Fig3.png\|frame\|center\|<b>Figure 3:</b> [http://en.wikipedia.org/wiki/Amd AMD] [http://en.wikipedia.org/wiki/Radeon Radeon] HD 6900 Series Block Diagram]]		[[Image:OpenCL_Fig3.png\|frame\|center\|<b>Figure 3:</b> [http://en.wikipedia.org/wiki/Amd AMD] [http://en.wikipedia.org/wiki/Radeon Radeon] HD 6900 Series Block Diagram]]

← Older revision		Revision as of 21:39, 19 February 2011
Line 182:		Line 182:
	As can be seen from Table 1, [[#Definitions\|GPUs]] can have a wide range of parameters, which often lead to performance differences. The top-of-the-line model like Radeon HD 6970 is equipped with more cores (PE), wider memory bus bandwidth and faster clock rate. As a result, it is much faster than a low-end model with significantly reduced configurations.		As can be seen from Table 1, [[#Definitions\|GPUs]] can have a wide range of parameters, which often lead to performance differences. The top-of-the-line model like Radeon HD 6970 is equipped with more cores (PE), wider memory bus bandwidth and faster clock rate. As a result, it is much faster than a low-end model with significantly reduced configurations.

	According to specification published by [http://en.wikipedia.org/wiki/Amd AMD][[#References\|<sup>[3]</sup>]], [http://en.wikipedia.org/wiki/Radeon Radeon] HD [[#Definitions\|GPU]] organization has significant similarity with [[#Definitions\|OpenCL]] platform model described above. The similarity can be seen from the figure below.		According to specification published by [http://en.wikipedia.org/wiki/Amd AMD][[#References\|<sup>[3]</sup>]], [http://en.wikipedia.org/wiki/Radeon Radeon] HD [[#Definitions\|GPU]] organization has significant similarity with [[#Definitions\|OpenCL]] platform model described above. The similarity can be seen from the figure below, where the DPP Array is essentially a group of CUs, local data share is simply a local memory region (in OpenCL terminology),

	[[Image:OpenCL_Fig3.png\|frame\|center\|<b>Figure 3:</b> [http://en.wikipedia.org/wiki/Amd AMD] [http://en.wikipedia.org/wiki/Radeon Radeon] HD 6900 Series Block Diagram]]		[[Image:OpenCL_Fig3.png\|frame\|center\|<b>Figure 3:</b> [http://en.wikipedia.org/wiki/Amd AMD] [http://en.wikipedia.org/wiki/Radeon Radeon] HD 6900 Series Block Diagram]]