CSC/ECE 506 Spring 2011/ch12 - Revision history

Dbharga at 06:30, 5 May 2011

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	Similar structure as the linear array, except, the ending nodes connect to each other, establishing a circular structure. The longest distance between two nodes is cut in half. A failure in any cable or device breaks the loop and can take down the entire network.		Similar structure as the linear array, except, the ending nodes connect to each other, establishing a circular structure. The longest distance between two nodes is cut in half. A failure in any cable or device breaks the loop and can take down the entire network.
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	Token Ring is an example of a ring topology. IBM Token Ring (802.5) networks imitate a ring at layer 2 but use a physical star at layer 1.		Token Ring is an example of a ring topology. IBM Token Ring (802.5) networks imitate a ring at layer 2 but use a physical star at layer 1 [16].
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Dbharga at 06:29, 5 May 2011

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	Similar structure as the linear array, except, the ending nodes connect to each other, establishing a circular structure. The longest distance between two nodes is cut in half. A failure in any cable or device breaks the loop and can take down the entire network.		Similar structure as the linear array, except, the ending nodes connect to each other, establishing a circular structure. The longest distance between two nodes is cut in half. A failure in any cable or device breaks the loop and can take down the entire network.
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	Token Ring is an example of a ring topology~~. 802.5 (Token Ring) networks do not use a ring topology at layer 1~~. IBM Token Ring (802.5) networks imitate a ring at layer 2 but use a physical star at layer 1.		Token Ring is an example of a ring topology. IBM Token Ring (802.5) networks imitate a ring at layer 2 but use a physical star at layer 1.
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Dbharga at 06:28, 5 May 2011

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	[[Image:mesh1.jpg]]		[[Image:mesh1.jpg]]
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	The mesh topology incorporates a unique network design in which each computer on the network connects to every other, creating a point-to-point connection between every device on the network. The purpose of the mesh design is to provide a high level of redundancy. If one network cable fails, the data always has an alternative path to get to its destination~~. Figure 6 shows the mesh topology~~.		The mesh topology incorporates a unique network design in which each computer on the network connects to every other, creating a point-to-point connection between every device on the network. The purpose of the mesh design is to provide a high level of redundancy. If one network cable fails, the data always has an alternative path to get to its destination.
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Dbharga at 06:27, 5 May 2011

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	[20] http://www.design-reuse.com/articles/23347/on-chip-network.html		[20] http://www.design-reuse.com/articles/23347/on-chip-network.html
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			[21] http://en.wikipedia.org/wiki/Clos_network
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			[22] http://en.wikipedia.org/wiki/Massive_parallel_processing
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			[23] http://en.wikipedia.org/wiki/Digital_signal_processor
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			[24] http://en.wikipedia.org/wiki/LAN

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Dbharga at 06:27, 5 May 2011

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	<h1>Definitions</h1>		<h1>Definitions</h1>
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	SIMD (single instruction, multiple-data). A processor which executes a single instruction simultaneously on multiple data locations.		Clos Network: A Clos network is a kind of multistage circuit switching network, first formalized by Charles Clos in 1953 [1], which represents a theoretical idealization of practical multi-stage telephone switching systems [21].
	MIMD (multiple instruction, multiple data). A processor which executes multiple instructions simultaneously on multiple data locations		<br>
			MPP: (Massively Parallel Processing) A massively parallel computer is a distributed memory computer system which consists of many individual nodes, each of which is essentially an independent computer in itself, and in turn consists of at least one processor, its own memory, and a link to the network that connects all the nodes together [22].
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			SIMD: (single instruction, multiple-data). A processor which executes a single instruction simultaneously on multiple data locations.
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			MIMD: (multiple instruction, multiple data). A processor which executes multiple instructions simultaneously on multiple data locations.
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			DSP: (Digital Signal Processor) DSP is a specialized microprocessor with an optimized architecture for the fast operational needs of digital signal processing [23].
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			LAN: (Local Area Network) LAN is a computer network that connects computers and devices in a limited geographical area such as home, school, computer laboratory or office building .[24]

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Dbharga at 06:12, 5 May 2011

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	These components work together to deliver data.		These components work together to deliver data.
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	Interconnection networks are used in most of the digital systems that are large enough to have two components to connect. The most common examples are the computer systems and communication switches. In computer systems, they connect processors to memories and I/O devices to I/O controllers. In 1980s, most of the applications were served by a very simple interconnection networks, example, the multi-drop bus. However, this has changed. All high performance interconnections are performed by point to point interconnection networks rather then buses, and more systems that have historically been bus-based switch to networks every year. This is because of non-uniform performance scaling. The demand for interconnection performance is increasing with processor performance and network bandwidth. Buses are not able to keep up with the bandwidth demand, and point-to-point interconnection networks which both operate faster than buses and offer concurrency.		Interconnection networks are used in most of the digital systems that are large enough to have two components to connect. The most common examples are the computer systems and communication switches. In computer systems, they connect processors to memories and I/O devices to I/O controllers. In 1980s, most of the applications were served by a very simple interconnection networks, example, the multi-drop bus. However, this has changed. All high performance interconnections are performed by point to point interconnection networks rather then buses, and more systems that have historically been bus-based switch to networks every year. This is because of non-uniform performance scaling. The demand for interconnection performance is increasing with processor performance and network bandwidth. Buses are not able to keep up with the bandwidth demand, and point-to-point interconnection networks which both operate faster than buses and offer concurrency.

Dbharga at 06:10, 5 May 2011

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	<h1>Characteristics of Networks with p Processors</h1>		<h1>Characteristics of Networks with p Processors</h1>
	[[Image:chart-network.jpg]]		[[Image:chart-network.jpg]]


			<h1>Definitions</h1>
			<p>
			SIMD (single instruction, multiple-data). A processor which executes a single instruction simultaneously on multiple data locations.
			MIMD (multiple instruction, multiple data). A processor which executes multiple instructions simultaneously on multiple data locations
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	<h1>References</h1>		<h1>References</h1>

Dbharga at 06:08, 5 May 2011

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	<h1>Metrics for Interconnection Networks</h1>		<h1>Metrics for Interconnection Networks</h1>
	1.'''Diameter''': ~~longest~~ distance between two nodes in the network		1.'''Diameter''': Longest distance between two nodes in the network

	2.'''Bisection Width''': Minimum of wire cuts to divide the network in 2 halves. Examples		2.'''Bisection Width''': Minimum of wire cuts to divide the network in 2 halves. Examples

Dbharga at 06:04, 5 May 2011

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 [15] [http://www.top500.org TOP500 Supercomputing Sites]
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Dbharga at 06:01, 5 May 2011

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	1 Solihin ~~text~~		[1] Y. Solihin, Fundamentals of Parallel Computer Architecture. Madison: OmniPress, 20
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	2 [http://www.ssrc.ucsc.edu/Papers/hospodor-mss04.pdf Interconnection Architectures for Petabyte-Scale High-Performance Storage Systems]		[2] [http://www.ssrc.ucsc.edu/Papers/hospodor-mss04.pdf Interconnection Architectures for Petabyte-Scale High-Performance Storage Systems]
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	3 [http://www.diit.unict.it/~vcatania/COURSES/semm_05-06/DOWNLOAD/noc_routing02.pdf The Odd-Even Turn Model for Adaptive Routing]		[3] [http://www.diit.unict.it/~vcatania/COURSES/semm_05-06/DOWNLOAD/noc_routing02.pdf The Odd-Even Turn Model for Adaptive Routing]
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	4 [http://www.csm.ornl.gov/workshops/IAA-IC-Workshop-08/documents/wiki/dally_iaa_workshop_0708.pdf Interconnection Topologies:(Historical Trends and Comparisons)]		[4] [http://www.csm.ornl.gov/workshops/IAA-IC-Workshop-08/documents/wiki/dally_iaa_workshop_0708.pdf Interconnection Topologies:(Historical Trends and Comparisons)]
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	5 [http://dspace.upv.es/xmlui/bitstream/handle/10251/2603/tesisUPV2824.pdf?sequence=1 Efficient mechanisms to provide fault tolerance in interconnection networks for PC clusters, José Miguel Montañana Aliaga.]		[5] [http://dspace.upv.es/xmlui/bitstream/handle/10251/2603/tesisUPV2824.pdf?sequence=1 Efficient mechanisms to provide fault tolerance in interconnection networks for PC clusters, José Miguel Montañana Aliaga.]
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	6 ~~[http://web~~.~~ebscohost~~.~~com~~.~~www~~.~~lib~~.~~ncsu~~.~~edu~~:~~2048/ehost/pdfviewer/pdfviewer?vid=2&hid=15&sid=72e3828d-3cb1-42b9-8198~~-~~5c1e974ea53f@sessionmgr4 Adaptive Fault Tolerant Routing Algorithm~~ for ~~Tree~~-~~Hypercube Multicomputer~~, ~~Qatawneh Mohammad]~~		[6] M. B. Taylor, W. Lee, S. Amarasinghe, and A. Agarwal. Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures.In International Symposium on High-Performance Computer Architecture (HPCA), pages 341–353, Anaheim, California,2003.
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	7 [http://www.top500.org TOP500 Supercomputing Sites]		[7] P. Gratz, C. Kim, R. McDonald, S. Keckler, and D. Burger. Implementation and Evaluation of On-Chip Network Architectures.In International Conference on Computer Design (ICCD), 2006.
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			[8] S. Vangal et al. An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. In IEEE Int'l Solid-State Circuits Conf., Digest of Tech. Papers(ISSCC), 2007.
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			[9] A. Agarwal, L. Bao, J. Brown, B. Edwards, M. Mattina, C.-C. Miao, C. Ramey, and D. Wentzlaff. Tile Processor: Embedded Multicore for Networking and Multimedia. In Hot Chips 19, Stanford, CA, Aug. 2007.
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			[10] http://en.wikipedia.org/wiki/Cray_X1.
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			[11] http://en.wikipedia.org/wiki/SGI_Origin_2000
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			[12] http://www.free-computer-tips.info/networking-tips/mesh-topology-tree-topology-and-hybrid-topology.html
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			[13] http://en.wikipedia.org/wiki/Fat_tree
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			[14] [http://web.ebscohost.com.www.lib.ncsu.edu:2048/ehost/pdfviewer/pdfviewer?vid=2&hid=15&sid=72e3828d-3cb1-42b9-8198-5c1e974ea53f@sessionmgr4 Adaptive Fault Tolerant Routing Algorithm for Tree-Hypercube Multicomputer, Qatawneh Mohammad]
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			[15] [http://www.top500.org TOP500 Supercomputing Sites]
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