CSC/ECE 506 Spring 2011/6a ms - Revision history

Mdsakalu: /* Prefetching */

2011-04-22T20:30:19Z

Prefetching

← Older revision		Revision as of 20:30, 22 April 2011
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	One way to solve the cache coherency problem is to simply drop prefetch write requests for shared data. This way prefetching can't mess up cache coherency, but will still give reads a performance boost. This solution is not good in write heavy applications, as much of the data will not be prefetched.<sup><span id="4body">[[#4foot\|[4]]]</span></sup>		One way to solve the cache coherency problem is to simply drop prefetch write requests for shared data. This way prefetching can't mess up cache coherency, but will still give reads a performance boost. This solution is not good in write heavy applications, as much of the data will not be prefetched.<sup><span id="4body">[[#4foot\|[4]]]</span></sup>

	===Costs and benefits===		==Costs and benefits==
	While prefetching schemes are harder to implement for parallel architectures, they can still provide a performance boost for some workloads. Other workloads, however, will suffer from prefetching.		While prefetching schemes are harder to implement for parallel architectures, they can still provide a performance boost for some workloads. Other workloads, however, will suffer from prefetching.

Mdsakalu: /* Prefetching in parallel architectures */

2011-04-22T20:27:10Z

Prefetching in parallel architectures

← Older revision		Revision as of 20:27, 22 April 2011
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	An Intel study of the effects of prefetching on the performance of a medical imaging application illustrates the varying levels of performance that prefetching can achieve. Intel studied combinations of hardware and software prefetching on their Core 2 Duo processor and how it affected to performance of a medical imaging application. For some workloads, hardware prefetching gave the best performance, and for others software prefetching gave the best performance. In some cases, prefetching actually reduced performance compared to having no prefetching at all.<sup><span id="7body">[[#7foot\|[7]]]</span></sup> The figure below summarizes the results of Intel's study.		An Intel study of the effects of prefetching on the performance of a medical imaging application illustrates the varying levels of performance that prefetching can achieve. Intel studied combinations of hardware and software prefetching on their Core 2 Duo processor and how it affected to performance of a medical imaging application. For some workloads, hardware prefetching gave the best performance, and for others software prefetching gave the best performance. In some cases, prefetching actually reduced performance compared to having no prefetching at all.<sup><span id="7body">[[#7foot\|[7]]]</span></sup> The figure below summarizes the results of Intel's study.

			[[Image:prefetch-results.png\|frame\|center\|Comparison of rendering times for four data prefetching scenarios (times are relative to "Hardware Prefetch/No Software Prefetch" scenario)<sup><span id="7body">[[#7foot\|[7]]]</span></sup>]]

	=References=		=References=

Mdsakalu: /* Prefetching in parallel architectures */

2011-04-22T20:25:18Z

Prefetching in parallel architectures

← Older revision		Revision as of 20:25, 22 April 2011
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	While prefetching schemes are harder to implement for parallel architectures, they can still provide a performance boost for some workloads. Other workloads, however, will suffer from prefetching.		While prefetching schemes are harder to implement for parallel architectures, they can still provide a performance boost for some workloads. Other workloads, however, will suffer from prefetching.

	An Intel study of the effects of prefetching on the performance of a medical imaging application illustrates the varying levels of performance that prefetching can achieve. Intel studied combinations of hardware and software prefetching on their Core 2 Duo processor and how it affected to performance of a medical imaging application. For some workloads, hardware prefetching gave the best performance, and for others software prefetching gave the best performance. In some cases, prefetching actually reduced performance compared to having no prefetching at all.		An Intel study of the effects of prefetching on the performance of a medical imaging application illustrates the varying levels of performance that prefetching can achieve. Intel studied combinations of hardware and software prefetching on their Core 2 Duo processor and how it affected to performance of a medical imaging application. For some workloads, hardware prefetching gave the best performance, and for others software prefetching gave the best performance. In some cases, prefetching actually reduced performance compared to having no prefetching at all.<sup><span id="7body">[[#7foot\|[7]]]</span></sup> The figure below summarizes the results of Intel's study.

	=References=		=References=

Mdsakalu: /* References */

2011-04-22T20:23:58Z

References

← Older revision		Revision as of 20:23, 22 April 2011
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	<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>		<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>
	<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>		<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>
	<span id="6foot">[[#6body\|6.]]</span> http://apt.cs.man.ac.uk/COMP60012/UoM-COMP60012-2009-slides-day1-7.pdf		<span id="6foot">[[#6body\|6.]]</span> http://apt.cs.man.ac.uk/COMP60012/UoM-COMP60012-2009-slides-day1-7.pdf<br>
			<span id="7foot">[[#7body\|7.]]</span> ftp://download.intel.com/technology/advanced_comm/315256.pdf

Mdsakalu: /* Prefetching */

2011-04-22T20:23:16Z

Prefetching

← Older revision		Revision as of 20:23, 22 April 2011
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	One way to solve the cache coherency problem is to simply drop prefetch write requests for shared data. This way prefetching can't mess up cache coherency, but will still give reads a performance boost. This solution is not good in write heavy applications, as much of the data will not be prefetched.<sup><span id="4body">[[#4foot\|[4]]]</span></sup>		One way to solve the cache coherency problem is to simply drop prefetch write requests for shared data. This way prefetching can't mess up cache coherency, but will still give reads a performance boost. This solution is not good in write heavy applications, as much of the data will not be prefetched.<sup><span id="4body">[[#4foot\|[4]]]</span></sup>

			===Costs and benefits===
			While prefetching schemes are harder to implement for parallel architectures, they can still provide a performance boost for some workloads. Other workloads, however, will suffer from prefetching.

			An Intel study of the effects of prefetching on the performance of a medical imaging application illustrates the varying levels of performance that prefetching can achieve. Intel studied combinations of hardware and software prefetching on their Core 2 Duo processor and how it affected to performance of a medical imaging application. For some workloads, hardware prefetching gave the best performance, and for others software prefetching gave the best performance. In some cases, prefetching actually reduced performance compared to having no prefetching at all.

	=References=		=References=

Mdsakalu: /* References */

2011-04-15T00:39:58Z

References

← Older revision		Revision as of 00:39, 15 April 2011
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	<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>		<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>
	<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>		<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>
			<span id="6foot">[[#6body\|6.]]</span> http://apt.cs.man.ac.uk/COMP60012/UoM-COMP60012-2009-slides-day1-7.pdf

Mdsakalu: /* Write Miss Policies */

2011-04-15T00:39:36Z

Write Miss Policies

← Older revision		Revision as of 00:39, 15 April 2011
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	'''Write-validate''' This policy is formed by the combination of no-fetch-on-write, write allocate, and no-write-invalidate. In this policy, a write causes no fetch of data and only the written data is marked valid. This is useful in situations where data is read while other data is being written. <sup><span id="2body">[[#2foot\|[2]]]</span></sup>		'''Write-validate''' This policy is formed by the combination of no-fetch-on-write, write allocate, and no-write-invalidate. In this policy, a write causes no fetch of data and only the written data is marked valid. This is useful in situations where data is read while other data is being written. <sup><span id="2body">[[#2foot\|[2]]]</span></sup>

	'''Write-around''' This policy is formed by the combination of no-fetch-on-write, no-write-allocate, and no-write-invalidate. It is called write-around because data goes directly to the next level of memory, around the cache. This policy is useful in situations where a processor makes many writes but rarely has to read data it has written.<sup><span id="2body">[[#2foot\|[2]]]</span></sup>		'''Write-around''' This policy is formed by the combination of no-fetch-on-write, no-write-allocate, and no-write-invalidate. It is called write-around because data goes directly to the next level of memory, around the cache. This policy is useful in situations where a processor makes many writes but rarely has to read data it has written.<sup><span id="2body">[[#2foot\|[2]]]</span></sup> Sun's Niagara architecture uses this policy.<sup><span id="6body">[[#6foot\|[6]]]</span></sup>

	'''Write-invalidate''' Since this policy does not have fetch-on-write or write-allocate, it is known as write-invalidate. It functions as described above.<sup><span id="2body">[[#2foot\|[2]]]</span></sup>		'''Write-invalidate''' Since this policy does not have fetch-on-write or write-allocate, it is known as write-invalidate. It functions as described above.<sup><span id="2body">[[#2foot\|[2]]]</span></sup>

Mdsakalu: /* References */

2011-04-15T00:32:21Z

References

← Older revision		Revision as of 00:32, 15 April 2011
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	<span id="3foot">[[#3body\|3.]]</span> Fundamentals of Parallel Computer Architecture by Yan Solihin <br>		<span id="3foot">[[#3body\|3.]]</span> Fundamentals of Parallel Computer Architecture by Yan Solihin <br>
	<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>		<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>
			<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>

Mdsakalu: /* Write Policy */

2011-04-15T00:31:48Z

Write Policy

← Older revision		Revision as of 00:31, 15 April 2011
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	'''Fetch-on-write''' This policy is the same as the write-allocate policy mentioned in the Solohin text.		'''Fetch-on-write''' This policy is the same as the write-allocate policy mentioned in the Solohin text. It is used by Intel architectures such as the Nehalem architecture.<sup><span id="5body">[[#5foot\|[5]]]</span></sup>

	'''Write-validate''' This policy is formed by the combination of no-fetch-on-write, write allocate, and no-write-invalidate. In this policy, a write causes no fetch of data and only the written data is marked valid. This is useful in situations where data is read while other data is being written. <sup><span id="2body">[[#2foot\|[2]]]</span></sup>		'''Write-validate''' This policy is formed by the combination of no-fetch-on-write, write allocate, and no-write-invalidate. In this policy, a write causes no fetch of data and only the written data is marked valid. This is useful in situations where data is read while other data is being written. <sup><span id="2body">[[#2foot\|[2]]]</span></sup>

Mdsakalu: /* Write Policy */

2011-04-15T00:23:20Z

Write Policy

← Older revision		Revision as of 00:23, 15 April 2011
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	==Write Hit Policies==		==Write Hit Policies==
	Write hit policies determine what to do when a write hits in cache, and are primarily concerned with reducing traffic.		Write hit policies determine what to do when a write hits in cache, and are primarily concerned with reducing traffic.<sup><span id="2body">[[#2foot\|[2]]]</span></sup>

	'''Write-through:''' In a write-through policy, changes written to the cache are immediately propagated to lower levels in the memory hierarchy. <sup><span id="3body">[[#3foot\|[3]]]</span></sup>		'''Write-through:''' In a write-through policy, changes written to the cache are immediately propagated to lower levels in the memory hierarchy. <sup><span id="3body">[[#3foot\|[3]]]</span></sup>
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	==Write Miss Policies==		==Write Miss Policies==
	Write miss policies determine what to do when a write misses in cache, and are primarily concerned with reducing latency. The Solihin text discusses write misses in terms of write-allocate versus write-no-allocate. However, write miss policies can be analyzed more in depth by looking at three different aspects of a write miss.		Write miss policies determine what to do when a write misses in cache, and are primarily concerned with reducing latency.<sup><span id="2body">[[#2foot\|[2]]]</span></sup> The Solihin text discusses write misses in terms of write-allocate versus write-no-allocate. However, write miss policies can be analyzed more in depth by looking at three different aspects of a write miss.

	'''Write-allocate''' In a write-allocate policy, writes that miss have a line allocated in the cache. Conversely, in write-no-allocate policy writes that miss have no like allocated for them in the cache. Subsequent reads of the written value have to wait for the value to be fetched from a lower level of memory<sup><span id="2body">[[#2foot\|[2]]]</span></sup>		'''Write-allocate''' In a write-allocate policy, writes that miss have a line allocated in the cache. Conversely, in write-no-allocate policy writes that miss have no like allocated for them in the cache. Subsequent reads of the written value have to wait for the value to be fetched from a lower level of memory<sup><span id="2body">[[#2foot\|[2]]]</span></sup>
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	Analyzing write miss policies using three criteria gives us more options that the single criteria mentioned in the Solihin text. The following graph shows the write miss rate reductions achieved for various benchmarks for the write-validate, write-around, and write-invalidate policies. A reduction is defined as a write miss that does not cause data to be fetched. We can see that they can be very effective depending on the application.		Analyzing write miss policies using three criteria gives us more options that the single criteria mentioned in the Solihin text. The following graph shows the write miss rate reductions achieved for various benchmarks for the write-validate, write-around, and write-invalidate policies. A reduction is defined as a write miss that does not cause data to be fetched.<sup><span id="2body">[[#2foot\|[2]]]</span></sup> We can see that they can be very effective depending on the application.

	[[Image:writemissreductions.png\|frame\|center\|Write miss rate reductions for 16B lines<sup><span id="2body">[[#2foot\|[2]]]</span></sup>]]		[[Image:writemissreductions.png\|frame\|center\|Write miss rate reductions for 16B lines<sup><span id="2body">[[#2foot\|[2]]]</span></sup>]]

← Older revision		Revision as of 20:23, 22 April 2011
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	<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>		<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>
	<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>		<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>
	<span id="6foot">[[#6body\|6.]]</span> http://apt.cs.man.ac.uk/COMP60012/UoM-COMP60012-2009-slides-day1-7.pdf		<span id="6foot">[[#6body\|6.]]</span> http://apt.cs.man.ac.uk/COMP60012/UoM-COMP60012-2009-slides-day1-7.pdf<br>
			<span id="7foot">[[#7body\|7.]]</span> ftp://download.intel.com/technology/advanced_comm/315256.pdf

← Older revision		Revision as of 00:39, 15 April 2011
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	<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>		<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>
	<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>		<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>
			<span id="6foot">[[#6body\|6.]]</span> http://apt.cs.man.ac.uk/COMP60012/UoM-COMP60012-2009-slides-day1-7.pdf

← Older revision		Revision as of 00:39, 15 April 2011
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	'''Write-validate''' This policy is formed by the combination of no-fetch-on-write, write allocate, and no-write-invalidate. In this policy, a write causes no fetch of data and only the written data is marked valid. This is useful in situations where data is read while other data is being written. <sup><span id="2body">[[#2foot\|[2]]]</span></sup>		'''Write-validate''' This policy is formed by the combination of no-fetch-on-write, write allocate, and no-write-invalidate. In this policy, a write causes no fetch of data and only the written data is marked valid. This is useful in situations where data is read while other data is being written. <sup><span id="2body">[[#2foot\|[2]]]</span></sup>

	'''Write-around''' This policy is formed by the combination of no-fetch-on-write, no-write-allocate, and no-write-invalidate. It is called write-around because data goes directly to the next level of memory, around the cache. This policy is useful in situations where a processor makes many writes but rarely has to read data it has written.<sup><span id="2body">[[#2foot\|[2]]]</span></sup>		'''Write-around''' This policy is formed by the combination of no-fetch-on-write, no-write-allocate, and no-write-invalidate. It is called write-around because data goes directly to the next level of memory, around the cache. This policy is useful in situations where a processor makes many writes but rarely has to read data it has written.<sup><span id="2body">[[#2foot\|[2]]]</span></sup> Sun's Niagara architecture uses this policy.<sup><span id="6body">[[#6foot\|[6]]]</span></sup>

	'''Write-invalidate''' Since this policy does not have fetch-on-write or write-allocate, it is known as write-invalidate. It functions as described above.<sup><span id="2body">[[#2foot\|[2]]]</span></sup>		'''Write-invalidate''' Since this policy does not have fetch-on-write or write-allocate, it is known as write-invalidate. It functions as described above.<sup><span id="2body">[[#2foot\|[2]]]</span></sup>

← Older revision		Revision as of 00:32, 15 April 2011
Line 314:		Line 314:
	<span id="3foot">[[#3body\|3.]]</span> Fundamentals of Parallel Computer Architecture by Yan Solihin <br>		<span id="3foot">[[#3body\|3.]]</span> Fundamentals of Parallel Computer Architecture by Yan Solihin <br>
	<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>		<span id="4foot">[[#4body\|4.]]</span> "A Taxonomy of Data Prefetching Mechanisms," Surendra Byna, Yong Chen, Xian-He Sun. http://www.cs.iit.edu/~chen/docs/ispan08-survey.pdf<br>
			<span id="5foot">[[#5body\|5.]]</span> http://software.intel.com/en-us/articles/performance-insights-to-intel-hyper-threading-technology/<br>