CSC/ECE 506 Spring 2010/chapter 10 - Revision history

Admin: /* '''Performance of Sequential Consistency on multiprocessors''' */

2010-05-04T20:16:20Z

'''Performance of Sequential Consistency on multiprocessors'''

← Older revision		Revision as of 20:16, 4 May 2010
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	'''Hardware optimization techniques:'''		'''Hardware optimization techniques:'''

	* '''Prefetching''' : ~~It is~~ hardware optimization technique in which the processor automatically prefetches ownership for any write operations that are delayed due to the program order requirement (e.g., by issuing prefetch-exclusive requests for any writes delayed		* '''Prefetching''' : A hardware optimization technique in which the processor automatically prefetches ownership for any write operations that are delayed due to the program order requirement (e.g., by issuing prefetch-exclusive requests for any writes delayed
	in the write buffer), thus partially overlapping the service of the delayed writes with the operations preceding them		in the write buffer), thus partially overlapping the service of the delayed writes with the operations preceding them
	in program order. This technique is only applicable to cache-based systems that use an invalidation-based protocol. This technique is suitable for statically scheduled processors.		in program order. This technique is only applicable to cache-based systems that use an invalidation-based protocol. This technique is suitable for statically scheduled processors.

	* '''Speculative Reads''' : ~~It is a~~ hardware optimization technique in which read operations that are delayed due to the program order requirement are serviced speculatively ahead of time. Sequential consistency is guaranteed by simply rolling back and reissuing the read and subsequent operations in the infrequent case that the read line gets invalidated or updated before the read could have been issued in a more straightforward implementation. This is suitable for dynamically scheduled processors since much		* '''Speculative Reads''' : A hardware optimization technique in which read operations that are delayed due to the program order requirement are serviced speculatively ahead of time. Sequential consistency is guaranteed by simply rolling back and reissuing the read and subsequent operations in the infrequent case that the read line gets invalidated or updated before the read could have been issued in a more straightforward implementation. This is suitable for dynamically scheduled processors since much
	of the roll back machinery is already present to deal with branch mispredictions.		of the roll back machinery is already present to deal with branch mispredictions.

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	'''Software Optimization techniques'''		'''Software Optimization techniques'''
	*'''Shasha and Snir's agorithm ''' : ~~It is a~~ compiler algorithm proposed by Dennis Shasha and Marc Snir ~~and~~ is used to detect when memory operations can be reordered without violating sequential consistency. It uses the technique where Sequential consistency can be enforced by delaying each access to shared memory until the previous access of the same processor has terminated. For performance reasons, it allows several accesses by the same processor to proceed concurrently. It performs an analysis to find a minimal set of delays that enforces sequential consistency. The analysis extends to interprocessor synchronization constraints and to code where blocks of operations have to execute atomically thus providing a new compiler optimization techniques for parallel languages that support shared variables.		*'''Shasha and Snir's agorithm ''' : A compiler algorithm proposed by Dennis Shasha and Marc Snir is used to detect when memory operations can be reordered without violating sequential consistency. It uses the technique where Sequential consistency can be enforced by delaying each access to shared memory until the previous access of the same processor has terminated. For performance reasons, it allows several accesses by the same processor to proceed concurrently. It performs an analysis to find a minimal set of delays that enforces sequential consistency. The analysis extends to interprocessor synchronization constraints and to code where blocks of operations have to execute atomically thus providing a new compiler optimization techniques for parallel languages that support shared variables.

	In detail implementation of this algorithm can be studied from the paper : '''[http://portal.acm.org/citation.cfm?id=42277 Efficient and correct execution of parallel programs that share memory]'''		In detail implementation of this algorithm can be studied from the paper : '''[http://portal.acm.org/citation.cfm?id=42277 Efficient and correct execution of parallel programs that share memory]'''

Rnramana: /* '''Different Relaxed consistency Models''' */

2010-04-20T05:07:40Z

'''Different Relaxed consistency Models'''

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	Apart from the program order relaxation, some of these models also '''relax the write atomicity''' requirement. <br />		Apart from the program order relaxation, some of these models also '''relax the write atomicity''' requirement. <br />
	#'''Read others’ write early''': allow a read to return the value of another processor’s write before the write is made visible to all other processors. This relaxation only applies to cache-based systems. <br />		#'''Read others’ write early''': allow a read to return the value of another processor’s write before the write is made visible to all other processors. This relaxation only applies to cache-based systems. <br />
	Let us consider an example to illustrate this: <br />		Let us consider an example from [http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt Memory Consistency Models, by Sarita Adve] to illustrate this: <br />

	[[Image:ro0.jpg]]<br />		[[Image:ro0.jpg]]<br />
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	#'''Read own write early''': a processor is allowed to read the value of its own previous write before the write is made visible to other processors. <br />		#'''Read own write early''': a processor is allowed to read the value of its own previous write before the write is made visible to other processors. <br />

	Example: <br />		Example from [http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt Memory Consistency Models, by Sarita Adve]: <br />

	[[Image:rb1.jpg]] <br />		[[Image:rb1.jpg]] <br />

Rnramana: /* '''References''' */

2010-04-20T05:06:36Z

'''References'''

Rnramana: /* '''References''' */

2010-04-20T05:00:27Z

'''References'''

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	[17] [http://www.cs.rochester.edu/research/cashmere/SC95/lazeag.html Lazy v. Eager Release Consistency]<br />		[17] [http://www.cs.rochester.edu/research/cashmere/SC95/lazeag.html Lazy v. Eager Release Consistency]<br />
	[18] [http://infoscience.epfl.ch/record/55789/files/isca92.ps.pdf Lazy Release Consistency for Software Distributed Shared Memory]<br />		[18] [http://infoscience.epfl.ch/record/55789/files/isca92.ps.pdf Lazy Release Consistency for Software Distributed Shared Memory]<br />
	[19] [www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt Memory Consistency Models, by Sarita Adve]<br />		[19] [http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt Memory Consistency Models, by Sarita Adve]<br />

Rnramana: /* '''References''' */

2010-04-20T04:59:55Z

'''References'''

Rnramana: /* '''References''' */

2010-04-20T04:55:31Z

'''References'''

← Older revision		Revision as of 04:55, 20 April 2010
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	='''References'''=		='''References'''=
	# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.5.7132&rep=rep1&type=pdf Speculative Sequential Consistency with Little Custom Storage]		[1] [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.5.7132&rep=rep1&type=pdf Speculative Sequential Consistency with Little Custom Storage]
	# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.3128&rep=rep1&type=pdf Two techniques to enhance the performance of memory consistency models]		[2] [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.3128&rep=rep1&type=pdf Two techniques to enhance the performance of memory consistency models]
	# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.47.8185&rep=rep1&type=pdf Optimizing parallel SPMD programs]		# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.47.8185&rep=rep1&type=pdf Optimizing parallel SPMD programs]
	# [http://portal.acm.org/citation.cfm?id=42277 Efficient and correct execution of parallel programs that share memory]		# [http://portal.acm.org/citation.cfm?id=42277 Efficient and correct execution of parallel programs that share memory]

Rnramana: /* '''Different Relaxed consistency Models''' */

2010-04-20T04:53:01Z

'''Different Relaxed consistency Models'''

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	We see that in P3, Read A returns zero while it should have been 1. This is because A was read before the P1's write to A had propagated to P3.<br />		We see that in P3, Read A returns zero while it should have been 1. This is because A was read before the P1's write to A had propagated to P3.<br />

	#'''Read own write early''': a processor is allowed to read the value of its own previous write before the write is made visible to other processors. This can happen if read early from write buffer. <br />		#'''Read own write early''': a processor is allowed to read the value of its own previous write before the write is made visible to other processors. <br />

			Example: <br />

			[[Image:rb1.jpg]] <br />

			This can happen if Flag1 is read early from write buffer, when read is re-ordered with respect to write.<br />

	All of the above models provide safety net that allow programmers to enforce the required constraints for achieving correctness. All models also maintain uniprocessor data and control dependences, and write serialization.		All of the above models provide safety net that allow programmers to enforce the required constraints for achieving correctness. All models also maintain uniprocessor data and control dependences, and write serialization.

Rnramana: /* '''Different Relaxed consistency Models''' */

2010-04-20T04:49:09Z

'''Different Relaxed consistency Models'''

← Older revision		Revision as of 04:49, 20 April 2010
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	Apart from the program order relaxation, some of these models also '''relax the write atomicity''' requirement. <br />		Apart from the program order relaxation, some of these models also '''relax the write atomicity''' requirement. <br />
	#'''Read others’ write early''': allow a read to return the value of another processor’s write before the write is made visible to all other processors. This relaxation only applies to cache-based systems. <br />		#'''Read others’ write early''': allow a read to return the value of another processor’s write before the write is made visible to all other processors. This relaxation only applies to cache-based systems. <br />
	Let us consider an example to illustrate this:		Let us consider an example to illustrate this: <br />

	~~Initially A = B = 0 <br />~~		[[Image:ro0.jpg]]<br />
	~~P1 P2 P3 <br />~~
	~~A = 1 while (A != 1) ; while (B != 1) ; <br />~~
	~~B = 1; tmp = A~~ <br />

	Let us see what happens if read returns new value before all copies see it. Below, (Write, A, 1) means the operation write on A returns 1 and (Read, A, 1) means the operation Read on A returns 1.		Let us see what happens if read returns new value before all copies see it. Below, (Write, A, 1) means the operation write on A returns 1 and (Read, A, 1) means the operation Read on A returns 1.

	~~P1 P2 P3 <br />~~		[[Image:ro1.jpg]]<br />
	~~Write, A, 1 <br />~~
	~~Read, A, 1 <br />~~
	~~Write, B, 1 <br />~~
	~~Read, B, 1 <br />~~
	~~Read, A, 0~~ <br />

	We see that in P3, Read A returns zero while it should have been 1. This is because A was read before the P1's write to A had propagated to P3.<br />		We see that in P3, Read A returns zero while it should have been 1. This is because A was read before the P1's write to A had propagated to P3.<br />

Rnramana: /* '''Different Relaxed consistency Models''' */

2010-04-20T04:38:06Z

'''Different Relaxed consistency Models'''

@@ Line 65: / Line 65: @@
 Apart from the program order relaxation, some of these models also '''relax the write atomicity''' requirement. <br />
 #'''Read others’ write early''':  allow a read to return the value of another processor’s write before the write is made visible to all other processors. This relaxation only applies to cache-based systems. <br />
-#'''Read own write early''':  a processor is allowed to read the value of its own previous write before the write is made visible to other processors.<br />
+Let us consider an example to illustrate this:
 All of the above models provide safety net that allow programmers to enforce the required constraints for achieving correctness.  All models also maintain uniprocessor data and control dependences, and write serialization.

Rnramana: /* ''IBM PowerPC'' */

2010-04-19T02:24:59Z

''IBM PowerPC''

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	\|		\|
	\|		\|
	\| Y		\| Yes
	\|		\|
	\|-		\|-
	\| IBM 370		\| IBM 370
	\| Y		\| Yes
	\|		\|
	\|		\|
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	\|-		\|-
	\| Total Store Ordering		\| Total Store Ordering
	\| Y		\| Yes
	\|		\|
	\|		\|
	\|		\|
	\| Y		\| Yes
	\| RMW		\| RMW
	\|-		\|-
	\| PC		\| PC
	\| Y		\| Yes
	\|		\|
	\|		\|
	\| Y		\| Yes
	\| Y		\| Yes
	\| RMW		\| RMW
	\|-		\|-
	\| PSO		\| PSO
	\| Y		\| Yes
	\| Y		\| Yes
	\|		\|
	\|		\|
	\| Y		\| Yes
	\| RMW, STBAR		\| RMW, STBAR
	\|-		\|-
	\| WO		\| WO
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\|		\|
	\| Y		\| Yes
	\| synchronization		\| synchronization
	\|-		\|-
	\| RCsc		\| RCsc
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\|		\|
	\| Y		\| Yes
	\| release, acquire, nsync, RMW		\| release, acquire, nsync, RMW
	\|-		\|-
	\| RCpc		\| RCpc
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\| release, acquire, nsync, RMW		\| release, acquire, nsync, RMW
	\|-		\|-
	\| Alpha		\| Alpha
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\|		\|
	\| Y		\| Yes
	\| MB, WMB		\| MB, WMB
	\|-		\|-
	\| RMO		\| RMO
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\|		\|
	\| Y		\| Yes
	\| MEMBARs		\| MEMBARs
	\|-		\|-
	\|PowerPC		\|PowerPC
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\| Y		\| Yes
	\| Sync		\| Sync
	\|}		\|}

← Older revision		Revision as of 05:06, 20 April 2010
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	='''References'''=		='''References'''=
	~~[1]~~ [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.5.7132&rep=rep1&type=pdf Speculative Sequential Consistency with Little Custom Storage] <br />		# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.5.7132&rep=rep1&type=pdf Speculative Sequential Consistency with Little Custom Storage] <br />
	~~[2]~~ [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.3128&rep=rep1&type=pdf Two techniques to enhance the performance of memory consistency models] <br />		# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.3128&rep=rep1&type=pdf Two techniques to enhance the performance of memory consistency models] <br />
	~~[3]~~ [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.47.8185&rep=rep1&type=pdf Optimizing parallel SPMD programs]<br />		# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.47.8185&rep=rep1&type=pdf Optimizing parallel SPMD programs]<br />
	~~[4]~~ [http://portal.acm.org/citation.cfm?id=42277 Efficient and correct execution of parallel programs that share memory]<br />		# [http://portal.acm.org/citation.cfm?id=42277 Efficient and correct execution of parallel programs that share memory]<br />
	~~[5]~~ [http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf Shared Memory Consistency Models]<br />		# [http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf Shared Memory Consistency Models]<br />
	~~[6]~~ [http://portal.acm.org/citation.cfm?id=193889&dl=GUIDE&coll=GUIDE&CFID=84028355&CFTOKEN=32262273 Designing Memory Consistency Models For Shared-Memory Multiprocessors]<br />		# [http://portal.acm.org/citation.cfm?id=193889&dl=GUIDE&coll=GUIDE&CFID=84028355&CFTOKEN=32262273 Designing Memory Consistency Models For Shared-Memory Multiprocessors]<br />
	~~[7]~~ [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.52.9935&rep=rep1&type=pdf Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors]<br />		# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.52.9935&rep=rep1&type=pdf Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors]<br />
	~~[8]~~ [http://ce.et.tudelft.nl/publicationfiles/915_463_bos.pdf Performance Benefits of Relaxed Memory Consistency for Process Network Applications]<br />		# [http://ce.et.tudelft.nl/publicationfiles/915_463_bos.pdf Performance Benefits of Relaxed Memory Consistency for Process Network Applications]<br />
	~~[9]~~ [http://www.cesr.ncsu.edu/solihin/Main.html Fundamentals of Parallel Computer Architecture by Yan Solihin]<br />		# [http://www.cesr.ncsu.edu/solihin/Main.html Fundamentals of Parallel Computer Architecture by Yan Solihin]<br />
	~~[10]~~ [http://www.cs.wisc.edu/multifacet/papers/computer98_sccase.pdf Multiprocessors Should Support Simple Memory-Consistency Models]<br />		# [http://www.cs.wisc.edu/multifacet/papers/computer98_sccase.pdf Multiprocessors Should Support Simple Memory-Consistency Models]<br />
	~~[11]~~ [http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf Technical Report by Kourosh Gharachorloo on Memory Consistency Models for shared-memory Multiprocessors]<br />		# [http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf Technical Report by Kourosh Gharachorloo on Memory Consistency Models for shared-memory Multiprocessors]<br />
	~~[12]~~ [http://cs.gmu.edu/cne/modules/dsm/green/memcohe.html Consistency Models]<br />		# [http://cs.gmu.edu/cne/modules/dsm/green/memcohe.html Consistency Models]<br />
	~~[13]~~ [http://www.barroso.org/publications/delayed.pdf Delayed Consistency and Its Effects on the Miss Rate of Parallel Programs]<br />		# [http://www.barroso.org/publications/delayed.pdf Delayed Consistency and Its Effects on the Miss Rate of Parallel Programs]<br />
	~~[14]~~ [http://delivery.acm.org.www.lib.ncsu.edu:2048/10.1145/230000/224398/a61-kontothanassis.html?key1=224398&key2=6529911721&coll=ACM&dl=ACM&CFID=140829&CFTOKEN=60032635 Lazy Release Consistency for Hardware-Coherent Multiprocessors]<br />		# [http://delivery.acm.org.www.lib.ncsu.edu:2048/10.1145/230000/224398/a61-kontothanassis.html?key1=224398&key2=6529911721&coll=ACM&dl=ACM&CFID=140829&CFTOKEN=60032635 Lazy Release Consistency for Hardware-Coherent Multiprocessors]<br />
	~~[15]~~ [http://infoscience.epfl.ch/record/55790/files/sosp91.ps.pdf Implementation and Performance of Munin]<br />		# [http://infoscience.epfl.ch/record/55790/files/sosp91.ps.pdf Implementation and Performance of Munin]<br />
	~~[16]~~ [http://www.springerlink.com/content/mg141q86k2112788/fulltext.pdf?page=1 Munin: Distributed Shared Memory Using Multi-Protocol Release Consistency]<br />		# [http://www.springerlink.com/content/mg141q86k2112788/fulltext.pdf?page=1 Munin: Distributed Shared Memory Using Multi-Protocol Release Consistency]<br />
	~~[17]~~ [http://www.cs.rochester.edu/research/cashmere/SC95/lazeag.html Lazy v. Eager Release Consistency]<br />		# [http://www.cs.rochester.edu/research/cashmere/SC95/lazeag.html Lazy v. Eager Release Consistency]<br />
	~~[18]~~ [http://infoscience.epfl.ch/record/55789/files/isca92.ps.pdf Lazy Release Consistency for Software Distributed Shared Memory]<br />		# [http://infoscience.epfl.ch/record/55789/files/isca92.ps.pdf Lazy Release Consistency for Software Distributed Shared Memory]<br />
	~~[19]~~ [http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt Memory Consistency Models, by Sarita Adve]<br />		# [http://www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt Memory Consistency Models, by Sarita Adve]<br />

← Older revision		Revision as of 04:59, 20 April 2010
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	='''References'''=		='''References'''=
	[1] [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.5.7132&rep=rep1&type=pdf Speculative Sequential Consistency with Little Custom Storage]		[1] [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.5.7132&rep=rep1&type=pdf Speculative Sequential Consistency with Little Custom Storage] <br />
	[2] [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.3128&rep=rep1&type=pdf Two techniques to enhance the performance of memory consistency models]		[2] [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.3128&rep=rep1&type=pdf Two techniques to enhance the performance of memory consistency models] <br />
	# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.47.8185&rep=rep1&type=pdf Optimizing parallel SPMD programs]		[3] [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.47.8185&rep=rep1&type=pdf Optimizing parallel SPMD programs]<br />
	# [http://portal.acm.org/citation.cfm?id=42277 Efficient and correct execution of parallel programs that share memory]		[4] [http://portal.acm.org/citation.cfm?id=42277 Efficient and correct execution of parallel programs that share memory]<br />
	# [http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf Shared Memory Consistency Models]		[5] [http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf Shared Memory Consistency Models]<br />
	# [http://portal.acm.org/citation.cfm?id=193889&dl=GUIDE&coll=GUIDE&CFID=84028355&CFTOKEN=32262273 Designing Memory Consistency Models For Shared-Memory Multiprocessors]		[6] [http://portal.acm.org/citation.cfm?id=193889&dl=GUIDE&coll=GUIDE&CFID=84028355&CFTOKEN=32262273 Designing Memory Consistency Models For Shared-Memory Multiprocessors]<br />
	# [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.52.9935&rep=rep1&type=pdf Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors]		[7] [http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.52.9935&rep=rep1&type=pdf Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors]<br />
	# [http://ce.et.tudelft.nl/publicationfiles/915_463_bos.pdf Performance Benefits of Relaxed Memory Consistency for Process Network Applications]		[8] [http://ce.et.tudelft.nl/publicationfiles/915_463_bos.pdf Performance Benefits of Relaxed Memory Consistency for Process Network Applications]<br />
	# [http://www.cesr.ncsu.edu/solihin/Main.html Fundamentals of Parallel Computer Architecture by Yan Solihin]		[9] [http://www.cesr.ncsu.edu/solihin/Main.html Fundamentals of Parallel Computer Architecture by Yan Solihin]<br />
	# [http://www.cs.wisc.edu/multifacet/papers/computer98_sccase.pdf Multiprocessors Should Support Simple Memory-Consistency Models]		[10] [http://www.cs.wisc.edu/multifacet/papers/computer98_sccase.pdf Multiprocessors Should Support Simple Memory-Consistency Models]<br />
	# [http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf Technical Report by Kourosh Gharachorloo on Memory Consistency Models for shared-memory Multiprocessors]		[11] [http://infolab.stanford.edu/pub/cstr/reports/csl/tr/95/685/CSL-TR-95-685.pdf Technical Report by Kourosh Gharachorloo on Memory Consistency Models for shared-memory Multiprocessors]<br />
	# [http://cs.gmu.edu/cne/modules/dsm/green/memcohe.html Consistency Models]		[12] [http://cs.gmu.edu/cne/modules/dsm/green/memcohe.html Consistency Models]<br />
	# [http://www.barroso.org/publications/delayed.pdf Delayed Consistency and Its Effects on the Miss Rate of Parallel Programs]		[13] [http://www.barroso.org/publications/delayed.pdf Delayed Consistency and Its Effects on the Miss Rate of Parallel Programs]<br />
	# [http://delivery.acm.org.www.lib.ncsu.edu:2048/10.1145/230000/224398/a61-kontothanassis.html?key1=224398&key2=6529911721&coll=ACM&dl=ACM&CFID=140829&CFTOKEN=60032635 Lazy Release Consistency for Hardware-Coherent Multiprocessors]		[14] [http://delivery.acm.org.www.lib.ncsu.edu:2048/10.1145/230000/224398/a61-kontothanassis.html?key1=224398&key2=6529911721&coll=ACM&dl=ACM&CFID=140829&CFTOKEN=60032635 Lazy Release Consistency for Hardware-Coherent Multiprocessors]<br />
	# [http://infoscience.epfl.ch/record/55790/files/sosp91.ps.pdf Implementation and Performance of Munin]		[15] [http://infoscience.epfl.ch/record/55790/files/sosp91.ps.pdf Implementation and Performance of Munin]<br />
	# [http://www.springerlink.com/content/mg141q86k2112788/fulltext.pdf?page=1 Munin: Distributed Shared Memory Using Multi-Protocol Release Consistency]		[16] [http://www.springerlink.com/content/mg141q86k2112788/fulltext.pdf?page=1 Munin: Distributed Shared Memory Using Multi-Protocol Release Consistency]<br />
	# [http://www.cs.rochester.edu/research/cashmere/SC95/lazeag.html Lazy v. Eager Release Consistency]		[17] [http://www.cs.rochester.edu/research/cashmere/SC95/lazeag.html Lazy v. Eager Release Consistency]<br />
	# [http://infoscience.epfl.ch/record/55789/files/isca92.ps.pdf Lazy Release Consistency for Software Distributed Shared Memory]		[18] [http://infoscience.epfl.ch/record/55789/files/isca92.ps.pdf Lazy Release Consistency for Software Distributed Shared Memory]<br />
			[19] [www.cs.cornell.edu/Courses/cs717/2001fa/lectures/sarita.ppt Memory Consistency Models, by Sarita Adve]<br />