Expertiza_Wiki - User contributions [en]

CSC/ECE 506 Fall 2007/wiki2 4 BV

2007-09-27T22:56:40Z

Vvijaya:

=MapReduce=
One of the major problems faced in the network world, is the need to classify huge amounts of data into easily understandable smaller data sets. It might be the problem of classifying hits for a website from different sources or classifying the frequency of occurrence of words in text, the problem involves analyzing large amounts of data into small understandable data sets.

''MapReduce'' is a programming model for processing large data sets. This was developed as a scalable, multiprocessing model by [http://www.google.com/about.html Google]. This model boasts of high scalability and high fault tolerance. ''MapReduce'' helps in ''mapping'' large data sets to smaller number of keys, thus ''reducing'' the data set itself to a more manageable proportion. More specifically, users specify a ''map'' function to process a key/value pair and generate a set of intermediate key/value pairs. The ''reduce'' function merges these intermediate key/values and generates the consolidated output.

Some of the examples, where ''MapReduce'' can be employed are:
*Distributed Grep
*Count of URL Access Frequency
*ReverseWeb-Link Graph
*Term-Vector per Host

=Steps of Parallelization=
The programs written based on this model can be parallelized and executed concurrently on a number of systems. The model provides the capability for partitioning of data, assignment to different processes and merging the results. 
[[Image:MapReduce03.JPG]] [http://209.85.163.132/papers/mapreduce-osdi04.pdf Execution Overview]

===Decomposition===
''Decomposition'' is a step that divides the problem into manageable tasks. In ''MapReduce'' the input data set is divided into M splits. Typically a master process takes care of the decomposition. The ''MapReduce'' algorithm tries to map a large dataset into a smaller number of key/value pairs.
The number of key/value pairs to be arrived at, will determine the size of the split. For example, the ''grep'' problem, which counts the number of occurrences of a specific word or a group of words in a document, the document is split into M equal parts. The size of each part is based on the number of distinct word(s)to be searched. Hence searching for larger group of words requires the document to be divided into smaller parts. 
Thus ''MapReduce'' provides an adaptive method for decomposing a problem.

===Assignment===
''Assignment'' is a step that assigns the related decomposed tasks to processes.
In ''MapReduce'' splits are assigned to idle map workers that generate R partial/complete outputs. These partial outputs are consolidated into a final result. In the ''grep'' problem, each worker is assigned a part of the document along with the word(s) to be searched. Each worker searches the part of the document assigned to it and generates a partial count of the occurrences. These partial counts from map workers are reduced into a final count by the reduce workers. The master is responsible for assigning M parts of the document and the R intermediate counts to idle workers. 
Thus ''MapReduce'' provides for load based task assignment which is beneficial in a scalable multiprocessor architecture.

===Orchestration===
''Orchestration'' is a step which groups the processes based on their interdependencies. The main purpose of this step is to reduce the synchronization and communication overhead between the processes. In the ''grep'' problem, the intermediate counts generated by the map workers represent an unsorted data set. By alphabetically sorting the intermediate word counts the reduce workers can be assigned with a coherent data set. This increases the probability that each reduce worker may work on a single or a small group of word counts. 
By providing an intermediate step for reduce ''MapReduce'' algorithm ensures that data locality is maintained. 
[[Image:MapReduce02.gif]] [http://labs.google.com/papers/mapreduce-osdi04-slides/index-auto-0008.html Parallel Execution] 

===Mapping===
''Mapping'' assigns the processes to different processors with an intent of minimizing the communication between them. Considering the ''grep'' problem, the master maps the document parts to processors executing map/reduce function. It is fair to assume that much of the time is spent in transferring the data across the network, from the master to the workers. One way of solving the problem is to, store replicas of the splits at different worker locations. The master can now assign the M splits in such a way that the replicas of the input document are local to the processor on which it is processed. This will eliminate the actual file transfer from the master to the map worker and thereby reducing the communication.

=Summary=
As seen from the ''grep'' example, ''MapReduce'' is a highly scalable and customizable algorithm for processing large data sets. In cases where, the data set is very large compared to the the number of available workers, the problem can be solved recursively. The final output can be fed back to the ''MapReduce'' engine by further refining the key/value pairs. Also, because of the user-customizable nature of the inputs, data and/or keys, any ''MapReduce'' solution is easily portable.

=References=
*[http://labs.google.com/papers/mapreduce.html Google Research publications]
*[http://en.wikipedia.org/wiki/MapReduce Wikipage on MapReduce]]

2007-09-11T03:57:18Z

Vvijaya: /* New Trends in Vector and Array Processing */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Block diagram of CRAY1 supercomputer at http://research.microsoft.com/users/gbell/CrayTalk/sld063.htm.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like :-

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

*http://en.wikipedia.org/wiki/PowerPC_G4

*http://en.wikipedia.org/wiki/Cell_microprocessor

*http://www.ausairpower.net/OSR-0600.html

*http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-11T03:57:09Z

Vvijaya: /* New Trends in Vector and Array Processing */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Block diagram of CRAY1 supercomputer at http://research.microsoft.com/users/gbell/CrayTalk/sld063.htm.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like :-

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

*http://en.wikipedia.org/wiki/PowerPC_G4

*http://en.wikipedia.org/wiki/Cell_microprocessor

*http://www.ausairpower.net/OSR-0600.html

*http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-11T03:56:49Z

Vvijaya: /* Description */

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-10T23:27:55Z

Vvijaya: /* New Trends in Vector and Array Processing */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Block diagram of CRAY1 supercomputer at http://research.microsoft.com/users/gbell/CrayTalk/sld063.htm

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like :-

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

*http://en.wikipedia.org/wiki/PowerPC_G4

*http://en.wikipedia.org/wiki/Cell_microprocessor

*http://www.ausairpower.net/OSR-0600.html

*http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-10T23:18:22Z

Vvijaya: /* Bibliography */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Block diagram of CRAY1 supercomputer at http://research.microsoft.com/users/gbell/CrayTalk/sld063.htm

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

*http://en.wikipedia.org/wiki/PowerPC_G4

*http://en.wikipedia.org/wiki/Cell_microprocessor

*http://www.ausairpower.net/OSR-0600.html

*http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-10T23:17:45Z

Vvijaya: /* Description */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Block diagram of CRAY1 supercomputer at http://research.microsoft.com/users/gbell/CrayTalk/sld063.htm

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

http://en.wikipedia.org/wiki/PowerPC_G4

http://en.wikipedia.org/wiki/Cell_microprocessor

http://www.ausairpower.net/OSR-0600.html

http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-10T23:17:30Z

Vvijaya: /* Description */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Block diagram of CRAY 1 supercomputer http://research.microsoft.com/users/gbell/CrayTalk/sld063.htm

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

http://en.wikipedia.org/wiki/PowerPC_G4

http://en.wikipedia.org/wiki/Cell_microprocessor

http://www.ausairpower.net/OSR-0600.html

http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-10T23:12:15Z

Vvijaya: /* Description */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

http://en.wikipedia.org/wiki/PowerPC_G4

http://en.wikipedia.org/wiki/Cell_microprocessor

http://www.ausairpower.net/OSR-0600.html

http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-10T23:12:05Z

Vvijaya: /* Description */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

http://en.wikipedia.org/wiki/PowerPC_G4

http://en.wikipedia.org/wiki/Cell_microprocessor

http://www.ausairpower.net/OSR-0600.html

http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-10T23:11:39Z

Vvijaya: /* Bibliography */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

Array and Vector Procesing

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

Recent Trends

http://en.wikipedia.org/wiki/PowerPC_G4

http://en.wikipedia.org/wiki/Cell_microprocessor

http://www.ausairpower.net/OSR-0600.html

http://www.cs.ucsc.edu/~mslater/papers/VectorProcessingG4.pdf

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-10T23:07:42Z

Vvijaya: /* Importance and Trends */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== New Trends in Vector and Array Processing ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the traditional problems of supercomputing, vector processing is finding applications in various other domains like

a. Gaming

Most of the code in gaming is a mixture of integer, floating point and vector calculations. This is best handled by a CPU with a vector unit. Dot
products are very critical to games as they are used to find out vector lengths, projections and transformations. Vector processing is best suited
for them.

Sony's third generation Play Stations called PS3 use Power PC based Cell processor having AltiVec vector processing units.

b. Image Processing

Image processing is a challenging domain: high computing power is required to calculate image adjustments in real time. These typically include
processing of pixel arrays and performing mathematical transforms (like Fast Four Transforms) on them. Vector processing helps in accelerating the
performance for such applications.

Apple Computers use the fourth generation of Power PC processors developed by Motorola ( MPC7400 series ) which incorporates the AltiVec model and is
one of the widely used embedded processors in this realm.

c. Signal processing applications like RADAR and SONAR

These processors can be harnessed well for signal processing applications. SONAR and RADAR are computationally intensive embedded applications
Vector processing architectures like AltiVec( from IBM, Motorola and Apple) deliver very well in the areas of graphics and multimedia which can stretch
even the current super scalar CPUs.

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:47:05Z

Vvijaya: /* Description */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and storing the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more throughput than serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements rather than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers.

Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research on applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:34:49Z

Vvijaya: /* Importance and Trends */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org. Horst D Simon, the Director of NERSC Center, gave a presentation on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers.

Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processors and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research on applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:28:41Z

Vvijaya: /* Future */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges like understanding, detecting and predicting the human influence on climate and modeling the earth system including atmosphere, ocean, land and their interactions require the aid of supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:20:17Z

Vvijaya: /* History */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each other through an interconnect that resembled a ring. Each element was provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:14:40Z

Vvijaya: /* Definition */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described as an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width. The pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:13:27Z

Vvijaya: /* Definition */

== Definition ==
Array Processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width and the pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:12:14Z

Vvijaya: /* Definition */

== Definition ==
Array processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting Instruction Level Parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width and the pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:11:31Z

Vvijaya: /* Definition */

== Definition ==
Array processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items at the same time. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting instruction level parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width and the pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:10:41Z

Vvijaya: /* Bibliography */

== Definition ==
Array processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting instruction level parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width and the pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://en.wikipedia.org/wiki/Vector_processor

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:09:08Z

Vvijaya: /* History */

== Definition ==
Array processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting instruction level parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width and the pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD (Single Instruction Multiple Data), which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:07:08Z

Vvijaya:

== Definition ==
Array processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting instruction level parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width and the pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD i.e. single instruction multiple data, which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T02:04:12Z

Vvijaya:

== Definition ==
Array processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory which execute the instruction. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting instruction level parallelism (ILP) where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of n-bit data elements each of a definite width and the pipelined units perform arithmetic operations on the data elements in parallel.

== History ==
Flynn’s Taxonomy classifies computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD i.e. single instruction multiple data, which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory capacity for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with a memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element 63)is directly connected to PE 0(Processing Element 0).

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched by the control unit will be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyzes, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at http://www.lib.ncsu.edu:2162/citation.cfm?id=808415&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

Vector Processing as the name itself suggests uses vectors i.e. a series of values or elements than a scalar i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional Units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect which is used for communication.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The pipelined functional units perform arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. Cray Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

More information on the same at http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_3.html.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at http://www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consisted of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It could run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions have streaming data and perform same operation on multiple elements.The functional units are deeply pipelined to exploit ILP (Instruction Level Parallelism). Multiple load/store units take advantage of this nature of inputs. Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at http://www.lib.ncsu.edu:2162/citation.cfm?id=956540&coll=portal&dl=ACM&CFID=28753767&CFTOKEN=45906295

== Future ==

Computational simulation is one of the areas which require supercomputing. The scientific challenges including understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions can only be done through supercomputers.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta.

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917

CSC/ECE 506 Fall 2007/wiki1 9 vr

2007-09-06T00:44:44Z

Vvijaya:

== Definition ==
Array processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory which execute the instruction. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting ILP where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of vector length n-bit data elements and the pipelined units perform arithmetic operations on the data elements in parallel.

== History ==

Flynn’s Taxonomy classifies the computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD i.e. single instruction multiple data, which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element) is directly connected to PE 0.

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and very relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

== Description ==

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched would be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyses, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

More information on the same at

Vector Processing as the name itself suggests uses VECTORS i.e. a series of values or elements than a SCALAR i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect with is used for communication between them.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The functional units are pipelined and they perform the arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. CRAY Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

== Importance and Trends ==

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack).
The listings are available at www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches.
Each node consists of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It can run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions are inherently data streaming and perform same operation on multiple elements. Multiple load/store units can take advantage of the nature of inputs. The functional units are deeply pipelined to exploit ILP 9instruction level parallelism.
Motorola has done a lot of research of applying these techniques for multimedia processing.

More information can be obtained at

== Future ==
Computational simulation is one of the areas which requires supercomputing. These scientific challenges include understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions to name a few.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.

== Bibliography ==

*Parallel Computer Architecture: A Hardware/Software Approach by David Culler, J.P. Singh, Anoop Gupta

*http://www.llnl.gov/computing/tutorials/parallel_comp/

*http://www.pcc.qub.ac.uk/tec/courses/cray/ohp/CRAY-slides_1.html

*http://www.cs.berkeley.edu/~pattrsn/252S98/Lec06-vector.pdf

*http://www-ugrad.cs.colorado.edu/~csci4576/VectorArch/VectorArch.html

*http://www.nersc.gov/~simon/Talks/Five_Trends.pdf

*http://www.cray.com/downloads/science/climate_modeling_flyer.pdf

*http://www.kuro5hin.org/story/2002/2/10/145957/917