Expertiza_Wiki - User contributions [en]

CSC/ECE 506 Fall 2007/wiki4 8 xk

2007-12-05T04:15:49Z

Tmhedber:

== Overview ==
Interconnection networks discussed in Parallel Computer Architecture lectures are somewhat simplified or idealized; in real parallel computers, network topologies often comprise modifications or amalgams of these basic structures. This article will examine some basic interconnection topologies and then describe the "realistic" topologies implemented in a few modern systems.

== Basic topologies ==
* '''Ring''' networks, as the name suggests, are organized into a ring structure, with each processing element ''P'' connected to its neighbors ''P'' - 1 and ''P'' + 1.
[[Image:Mesh_topology.jpg|frame|Mesh topology]]
* '''Mesh''' networks form grid-like structures in which each processing element ''P'' is connected to nodes ''P'' - 1 and ''P'' + 1, as well as "skipping" several nodes ahead and behind (i.e. connections to ''P'' - 4 and ''P'' + 4 in a mesh network with four nodes to a row).
* '''Hypercube''' networks form cubes with log2 ''n'' nodes to a side, where ''n'' is the total number of nodes.
[[Image:Barrel_shifter_topology.jpg|frame|Barrel shifter topology]]
* '''Barrel shifters''' are similar to mesh networks with the addition of connections from each node to nodes 2<super>''i''</super> ahead and behind that node (where ''i'' is any integer). For instance, node ''P'' would have connections to nodes ''P'' + 1, ''P'' + 2, ''P'' + 4, ''P'' + 8, etc., as well as to ''P'' - 1, ''P'' - 2, ''P'' - 4, ''P'' - 8, etc.

== Real-world implementations ==
Many modern supercomputers utilize proprietary interconnection schemes and therefore data on them are limited or difficult to find. The following list designates the interconnection network topologies used in various supercomputers for which such data are available.
* '''SGI Altix ICE 8200''': Infiniband (switched fabric topology)
* '''Red Storm''': Cray XT3 Interconnect (three-dimensional toroid)
* '''Blue Gene/L'''
** Three-dimensional toroid for inter-nodal peer-to-peer communication
** Collective (broadcast) network for one node to send messages to several other nodes simultaneously
** "Global barrier network" which performs a global OR operation over all nodes

== References ==
* [http://courses.ncsu.edu/csc506/common/lectures/notes/lec25.pdf ECE/CSC506 lecture notes]
* [http://top500.org/lists/2007/11 TOP500 Top 10 sites for November 2007]
* [http://www.research.ibm.com/journal/rd/492/gara.html Overview of the Blue Gene/L system architecture]

CSC/ECE 506 Fall 2007/wiki8 4 xk

2007-11-26T20:01:13Z

Tmhedber:

File:Barrel shifter topology.jpg

2007-11-26T20:00:33Z

Tmhedber: Diagram of barrel shifter topology for supercomputer interconnection networks

Diagram of barrel shifter topology for supercomputer interconnection networks

File:Mesh topology.jpg

2007-11-26T19:57:16Z

Tmhedber: Diagram of mesh topology for supercomputer interconnection networks

Diagram of mesh topology for supercomputer interconnection networks

CSC/ECE 506 Fall 2007/wiki8 4 xk

2007-11-26T19:51:20Z

Tmhedber:

== Overview ==
Interconnection networks discussed in Parallel Computer Architecture lectures are somewhat simplified or idealized; in real parallel computers, network topologies often comprise modifications or amalgams of these basic structures. This article will examine some basic interconnection topologies and then describe the "realistic" topologies implemented in a few modern systems.

== Basic topologies ==
* '''Ring''' networks, as the name suggests, are organized into a ring structure, with each processing element ''P'' connected to its neighbors ''P'' - 1 and ''P'' + 1.
* '''Mesh''' networks form grid-like structures in which each processing element ''P'' is connected to nodes ''P'' - 1 and ''P'' + 1, as well as "skipping" several nodes ahead and behind (i.e. connections to ''P'' - 4 and ''P'' + 4 in a mesh network with four nodes to a row).
* '''Hypercube''' networks form cubes with log2 ''n'' nodes to a side, where ''n'' is the total number of nodes.
* '''Barrel shifters''' are similar to mesh networks with the addition of connections from each node to nodes 2<super>''i''</super> ahead and behind that node (where ''i'' is any integer). For instance, node ''P'' would have connections to nodes ''P'' + 1, ''P'' + 2, ''P'' + 4, ''P'' + 8, etc., as well as to ''P'' - 1, ''P'' - 2, ''P'' - 4, ''P'' - 8, etc.

== Real-world implementations ==
Many modern supercomputers utilize proprietary interconnection schemes and therefore data on them are limited or difficult to find. The following list designates the interconnection network topologies used in various supercomputers for which such data are available.
* '''SGI Altix ICE 8200''': Infiniband (switched fabric topology)
* '''Red Storm''': Cray XT3 Interconnect (three-dimensional toroid)
* '''Blue Gene/L'''
** Three-dimensional toroid for inter-nodal peer-to-peer communication
** Collective (broadcast) network for one node to send messages to several other nodes simultaneously
** "Global barrier network" which performs a global OR operation over all nodes

== References ==
* [http://courses.ncsu.edu/csc506/common/lectures/notes/lec25.pdf ECE/CSC506 lecture notes]
* [http://top500.org/lists/2007/11 TOP500 Top 10 sites for November 2007]
* [http://www.research.ibm.com/journal/rd/492/gara.html Overview of the Blue Gene/L system architecture]

CSC/ECE 506 Fall 2007/wiki1 1 ab

2007-09-10T17:30:46Z

Tmhedber:

== Moore's Law in the Future==
In 1965, Gordon Moore famously observed a growth trend in microprocessor technology that has held true ever since. His prediction that microchip feature density would double every 18 months has proven largely correct despite the incredible changes the industry has seen since the 1960s. In some ways, the "law" predicted by Moore has been a self-fulfilling prophecy, pushing the industry to meet its Moore's Law "quota" and drive feature sizes down and clock rates up.

It is predicted that the Moore's Law trend will continue for some time. Chip manufacturers continue to make design improvements that perpetuate the continual increase in chip complexity.[http://www.washingtonpost.com/wp-dyn/content/article/2007/01/27/AR2007012700018.html] While increasing the number of transistors on a chip seems to directly impact the single-processor area of computing, it also has numerous implications in the multiprocessor regime. Of course, increased density yields increased performance in all types of computers, but it also allows for new types of parallel processors such as the now-common single-ship multi-core CPU. Incorporating parallel computing principles onto a single chip has made the benefits of parallelism more affordable even for everyday consumers, and this trend can be expected to continue.

[[Image:SIX0404LAW1A.gif]]

''From http://www.semiconductor.net/article/CA405656.html''

== Price vs. Performance ==
Affordability is always the bottom line in technology development; better performance is nearly always physically possible, but is limited by economic practicality. As multiprocessor architecture improves, however, ideas which were once unfeasible become more and more realistic. Large computing clusters made up of arrays of several average-to-high performance machines have led the affordability trends for some time.[http://lqcd.fnal.gov/trends.html] This is largely due to the fact that such clusters are comprised of readily-available computer systems in large quantities and can be assembled easily, without much architecture expertise.

As previously mentioned, single=chip parallel processors are also becoming the norm in the consumer PC market. As it becomes more and more difficult to increase clock rates past their current levels, architects are making up the difference by simply adding more processor cores to their chips. Quad-core CPUs are already available, but even larger numbers will be available in the near future.[http://techfreep.com/intel-80-cores-by-2011.htm]

== Conclusion ==
Ultimately, the same trends which have emerged since the development of the microprocessor show signs of continuing into the foreseeable future. Trends which have long applied to single-processor applications appear to scale proportionally when more processors are added to the implementation in a parallel fashion. However, there is a limit to how densely transistors can be produced on a chip, so Moore's Law will not hold indefinitely. Instead, multiprocessing will take over the majority of the performance gains. This will allow the end-user performance benefits of Moore's predictions to continue even when the root cause of the benefits has changed.

File:SIX0404LAW1A.gif

2007-09-10T17:23:13Z

Tmhedber: From http://www.semiconductor.net/article/CA405656.html

From http://www.semiconductor.net/article/CA405656.html

CSC/ECE 506 Fall 2007/wiki1 1 ab

2007-09-06T00:04:02Z

Tmhedber:

== Moore's Law in the Future==
In 1965, Gordon Moore famously observed a growth trend in microprocessor technology that has held true ever since. His prediction that microchip feature density would double every 18 months has proven largely correct despite the incredible changes the industry has seen since the 1960s. In some ways, the "law" predicted by Moore has been a self-fulfilling prophecy, pushing the industry to meet its Moore's Law "quota" and drive feature sizes down and clock rates up.

It is predicted that the Moore's Law trend will continue for some time. Chip manufacturers continue to make design improvements that perpetuate the continual increase in chip complexity.[http://www.washingtonpost.com/wp-dyn/content/article/2007/01/27/AR2007012700018.html] While increasing the number of transistors on a chip seems to directly impact the single-processor area of computing, it also has numerous implications in the multiprocessor regime. Of course, increased density yields increased performance in all types of computers, but it also allows for new types of parallel processors such as the now-common single-ship multi-core CPU. Incorporating parallel computing principles onto a single chip has made the benefits of parallelism more affordable even for everyday consumers, and this trend can be expected to continue.

== Price vs. Performance ==
Affordability is always the bottom line in technology development; better performance is nearly always physically possible, but is limited by economic practicality. As multiprocessor architecture improves, however, ideas which were once unfeasible become more and more realistic. Large computing clusters made up of arrays of several average-to-high performance machines have led the affordability trends for some time.[http://lqcd.fnal.gov/trends.html] This is largely due to the fact that such clusters are comprised of readily-available computer systems in large quantities and can be assembled easily, without much architecture expertise.

As previously mentioned, single=chip parallel processors are also becoming the norm in the consumer PC market. As it becomes more and more difficult to increase clock rates past their current levels, architects are making up the difference by simply adding more processor cores to their chips. Quad-core CPUs are already available, but even larger numbers will be available in the near future.[http://techfreep.com/intel-80-cores-by-2011.htm]

CSC/ECE 506 Fall 2007/wiki1 1 ab

2007-09-06T00:02:32Z

Tmhedber:

== Moore's Law ==
In 1965, Gordon Moore famously observed a growth trend in microprocessor technology that has held true ever since. His prediction that microchip feature density would double every 18 months has proven largely correct despite the incredible changes the industry has seen since the 1960s. In some ways, the "law" predicted by Moore has been a self-fulfilling prophecy, pushing the industry to meet its Moore's Law "quota" and drive feature sizes down and clock rates up.

It is predicted that the Moore's Law trend will continue for some time. Chip manufacturers continue to make design improvements that perpetuate the continual increase in chip complexity.[http://www.washingtonpost.com/wp-dyn/content/article/2007/01/27/AR2007012700018.html] While increasing the number of transistors on a chip seems to directly impact the single-processor area of computing, it also has numerous implications in the multiprocessor regime. Of course, increased density yields increased performance in all types of computers, but it also allows for new types of parallel processors such as the now-common single-ship multi-core CPU. Incorporating parallel computing principles onto a single chip has made the benefits of parallelism more affordable even for everyday consumers, and this trend can be expected to continue.

== Price vs. Performance ==
Affordability is always the bottom line in technology development; better performance is nearly always physically possible, but is limited by economic practicality. As multiprocessor architecture improves, however, ideas which were once unfeasible become more and more realistic. Large computing clusters made up of arrays of several average-to-high performance machines have led the affordability trends for some time.[http://lqcd.fnal.gov/trends.html] This is largely due to the fact that such clusters are comprised of readily-available computer systems in large quantities and can be assembled easily, without much architecture expertise.

As previously mentioned, single=chip parallel processors are also becoming the norm in the consumer PC market. As it becomes more and more difficult to increase clock rates past their current levels, architects are making up the difference by simply adding more processor cores to their chips. Quad-core CPUs are already available, but even larger numbers will be available in the near future.[http://techfreep.com/intel-80-cores-by-2011.htm]

CSC/ECE 506 Fall 2007/wiki1 1 ab

2007-09-05T23:48:36Z

Tmhedber: