Expertiza_Wiki - User contributions [en]

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-29T02:01:42Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

= Introduction =
Several cache technology which can expedite the speed of processing are used for modern processors over memory-CPU gap. Since the cache structure itself can affect the performance of the cache, to choose an appropriate structure is an important and a hard to solve problem. For example, generally bigger cache shows better performance. However due to cache pollution, the performance shows diminishing returns as the cache size goes bigger. Thus we have to choose an appropriate cache size. From this point, it might be valuable to look through the cache chracteristics of modern processors.

The cache structure can be determined by a few parameters such as cache size, replacement algorithm and associativity, and cache line size. While multi-core processors are introduced, the cache coherency also becomes issue and the coherency protocol such as MESI and MOESI affects the performance. In this psage, several cache parameters will be shown for modern multicore processors as well as for a couple of single-core processors.

= Cache sizes in multicore architectures =

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

= Conclusion =
Most of processors introduced nowadays have 32K or 64K data/instruction L1 cache which have 2, 4 or 8 set-associativity, although we can have many other sizes and associativity. The cache lines are either 64 or 128 bytes. MESI and MOESI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

= References =
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-29T02:01:24Z

Sykang: /* Introduction */

= Introduction =
Several cache technology which can expedite the speed of processing are used for modern processors over memory-CPU gap. Since the cache structure itself can affect the performance of the cache, to choose an appropriate structure is an important and a hard to solve problem. For example, generally bigger cache shows better performance. However due to cache pollution, the performance shows diminishing returns as the cache size goes bigger. Thus we have to choose an appropriate cache size. From this point, it might be valuable to look through the cache chracteristics of modern processors.

The cache structure can be determined by a few parameters such as cache size, replacement algorithm and associativity, and cache line size. While multi-core processors are introduced, the cache coherency also becomes issue and the coherency protocol such as MESI and MOESI affects the performance. In this psage, several cache parameters will be shown for modern multicore processors as well as for a couple of single-core processors.

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

= Conclusion =
Most of processors introduced nowadays have 32K or 64K data/instruction L1 cache which have 2, 4 or 8 set-associativity, although we can have many other sizes and associativity. The cache lines are either 64 or 128 bytes. MESI and MOESI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

= References =
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-29T01:10:26Z

Sykang: /* Conclusion */

= Introduction =
Several cache technology which can expedite the speed of processing are used for modern processors over memory-CPU gap. Since the cache structure itself can affect the performance of the cache, to choose the appropriate structure of cache is an important and hard to solve problem. For example, generally bigger cache shows better performance. However due to cache pollution, the performance shows diminishing returns as the cache size goes bigger. Thus we have to choose an appropriate cache size. Hence, it might be valuable to look through the cache chracteristics of modern processors.

The cache structure can be determined by a few parameters such as cache size, replacement algorithm and associativity, and cache line size. While multi-core processors are introduced, the cache coherency also becomes issue and the coherency protocol such as MESI and MOESI affects the performance. In this material, several cache parameters will be shown for modern multicore processors as well as a couple of single-core processors.

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

= Conclusion =
Most of processors introduced nowadays have 32K or 64K data/instruction L1 cache which have 2, 4 or 8 set-associativity, although we can have many other sizes and associativity. The cache lines are either 64 or 128 bytes. MESI and MOESI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

= References =
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-29T01:07:07Z

Sykang: /* Introduction */

= Introduction =
Several cache technology which can expedite the speed of processing are used for modern processors over memory-CPU gap. Since the cache structure itself can affect the performance of the cache, to choose the appropriate structure of cache is an important and hard to solve problem. For example, generally bigger cache shows better performance. However due to cache pollution, the performance shows diminishing returns as the cache size goes bigger. Thus we have to choose an appropriate cache size. Hence, it might be valuable to look through the cache chracteristics of modern processors.

The cache structure can be determined by a few parameters such as cache size, replacement algorithm and associativity, and cache line size. While multi-core processors are introduced, the cache coherency also becomes issue and the coherency protocol such as MESI and MOESI affects the performance. In this material, several cache parameters will be shown for modern multicore processors as well as a couple of single-core processors.

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

= Conclusion =
Most of processors introduced nowadays have 32K or 64K data/instruction L1 cache which have 2, 4 or 8 set-associativity. The cache lines are either 64 or 128 bytes. MESI and MOESI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

= References =
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-29T01:05:35Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

= Introduction =
Several cache technology which can expedite the speed of processing are used for modern processors over memory-CPU gap. Since the cache structure itself can affect the performance of the cache, to choose the appropriate structure of cache is an important and hard to solve problem. For example, generally bigger cache shows better performance. However due to cache pollution, the performance shows diminishing returns as the cache size goes bigger. Thus we have to choose an appropriate cache size. Hence, it might be valuable to look through the cache chracteristics of modern processors.

The cache structure can be determined by a few parameters such as cache size, cache type such direct mapped or set associative and so on, and cache line size. While multi-core processors are introduced, the cache coherency also becomes issue and the coherency protocol such as MESI and MOESI affects the performance. In this material, several cache parameters will be shown for modern multicore processors as well as a couple of single-core processors.

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

= Conclusion =
Most of processors introduced nowadays have 32K or 64K data/instruction L1 cache which have 2, 4 or 8 set-associativity. The cache lines are either 64 or 128 bytes. MESI and MOESI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

= References =
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-29T00:41:35Z

Sykang: /* Conclusion */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
Most of processors introduced nowadays have 32K or 64K data/instruction L1 cache which have 2, 4 or 8 set-associativity. The cache lines are either 64 or 128 bytes. MESI and MOESI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:21:35Z

Sykang: /* Conclusion */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
Most of processors introduced nowadays have 32K or 64K data/instruction L1 cache which have 2, 4 or 8 set-associativity. The cache lines are 64 or 128 bytes almostly. MESI and MOESI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:21:00Z

Sykang: /* Conclusion */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
Most of processors which are introduced nowadays have 32K or 64K data/instruction L1 cache which have 2, 4 or 8 set-associativity. The cache lines are 64 or 128 bytes almostly. MESI and MEOSI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:17:57Z

Sykang: /* Conclusion */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
Most of processors which are introduced nowadays use 4 or 8 set-associative cache for both data and instruction cache.
The cache lines is 64 bytes. MESI and MEOSI are the prevailed cache coherency protocol.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:09:59Z

Sykang: /* Conclusion */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
Most of processors use set-associative cache for both data and instruction cache, and use MESI or MEOSI cache coherency protocols.

From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:07:13Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:06:32Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16KB Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data, 32KB instruction L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:03:49Z

Sykang: /* References */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16K Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data (2-way associative), 32KB instruction (2-Way associative) L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:02:48Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16K Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 - 32 byte lines
| L1 - 32KB data (2-way associative), 32KB instruction (2-Way associative) L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T02:02:17Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 16 KB data, 16K Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 bytes lines<br/2>L2 -
| L1 - 32KB data (2-way associative), 32KB instruction (2-Way associative) L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-25T01:59:00Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - L2 -
| L1 - 16 KB data, 16K Instruction L2 - 256KB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 bytes lines<br/2>L2 -
| L1 - 32KB data (2-way associative), 32KB instruction (2-Way associative) L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==
From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 05 sa

2007-09-25T01:49:29Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 -
| L1 - 32KB data (2-way associative), 32KB instruction (2-Way associative) L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - L2 -
| L1 - 16 KB data, 16K Instruction L2 - 256KB
| L1 - L2 - 8 way
|
|-
| Intel Core Solo
| 2
| L1 - L2 -
| L1 - 32 KB data, 32KB Instruction L2 - 2MB
| L1 - L2 -
|
|}

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 05 sa

2007-09-25T01:47:35Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - L2 -
| L1 - 16 KB data, 16K Instruction L2 - 256KB
| L1 - L2 - 8 way
|
|-
| AMD K6 / K6 III
| 2
| L1 - 32 byte lines<br/2>L2 -
| L1 - 32KB data (2-way associative), 32KB instruction (2-Way associative) L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 05 sa

2007-09-25T01:45:45Z

Sykang: /* <center>Cache sizes in multicore architectures</center> */

=<center>Cache sizes in multicore architectures</center>=

''Topic'' - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron (marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core
| L1 - 2 way (Data and Instruction cache) L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium D
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Pentium Dual Core
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel Core 2 Duo
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Broadcom SiByte SB1250
| 2
| L1 - 32 byte lines L2 - 32 byte lines
| L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Sun Microsystems UltraSPARC IV
| 2
| L1 - 128byte lines L2 - 128 byte lines
| L1 - 64KB data, 32KB instruction L2 - up to 16MB
| L2 - 2 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| IBM Cell Processor
| 2
| Not Available
| L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB
| L1 - 2 way instruction, 4 way data L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| AMD Athlon 64
| 2
| L1 - 64 byte lines L2 - 64 byte lines
| L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB
| L1 - 2 way L2 - 16 way
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| Intel Pentium 4
| 2
| L1 - 64 byte lines L2 - 128 byte lines
| L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB
| L1 - 4 way L2 - 8 way
| Modified Exclusive Shared Invalid (MESI)
|-
| Intel PentiumIII 600
| 2
| L1 - L2 -
| L1 - 16 KB data, 16K Instruction L2 - 256KB
| L1 - L2 - 8 way
|
|-
| AMD K6 / K6 III
| 2
| L1 - 32 bytes lines<br/2>L2 -
| L1 - 32KB data (2-way associative), 32KB instruction (2-Way associative) L2 - 256KB
| L1 - 2 way L2 - 4 way
| Modified Exclusive Shared Invalid (MESI)
|}

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

[12] http://en.wikipedia.org/wiki/Cell_microprocessor

[13] http://techreport.com/articles.x/8236/2

[14] http://www.hardwaresecrets.com/article/481/9

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T23:16:16Z

Sykang: /* Cache size and characteristics of multi-core processors */

== Cache size and characteristics of multi-core processors ==

The following tables shows the current tide of the multicore processors's cache.

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

=== AMD ===
{| border="1" cellspacing="0"
!Processor
!L1 Cache
!L2 Cache
!L3 Cache
!Description
|-
!Opteron Server/Workstation
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!1 MB per core, 16-way associative
!
!Dual cores, introduced on 4/22/2005
|-
!Athlon64 X2 family
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!up to 1 MB per core, 16-way associative
!
!Dual cores, intoduced on 5/13/2005
|-
!Athlon64 FX
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!up to 1 MB per core, 16-way associative
!
!High performance desktop
|-
!Turion64 X2
!Total 256KB (128K per core)
!Total 1MB (512K per core)
!
!For Laptop
|}

=== Broadcom ===
* SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

=== IBM ===
* Cell
In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

* Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

* Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M

* Power5
Dual core
L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way

* PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol

=== Intel ===
* Core2 Quad

* Xeon Quad core
12/13/2006

* Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

* Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

* Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
* Core2 Duo
Xeon (x1xx) Dual core

* Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

* Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

* Itanium 2
Multi-core
Montecito
L1:32KB
L2:256KB
L3:up to 9MB

=== Stream Processors ===
* Strom-1 fmaily
40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction
96K VLIW instruction memory

=== Sun Microsystems ===
* UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

* UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

* UlatraSPARC T1
8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

=== ETC ===
ARM
MPCore container for ARM9 & ARM11
High-performance embedded and entertainment

PARISC
PA8800
L1: 1.5M Data 4-way associative + 1.5M Instruction 4-way associative, 2cycle
L2: 32M

CT3600
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

Cavium Networks
Octeon
CN38XX
16 MIPS cores
L1: 8K Data + 32K Instruction
L2: 1M shared, ECC protected
Other: 2K write buffer per every MIPS core

CN36XX
4 MIPS cores
L1: 8K Data + 32K Instruction
L2: 512K
Other: 2K write buffer per every MIPS core

== Cache size and characteristics of single-core processors ==

=== AMD ===

* Athlon 64
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T23:03:44Z

Sykang: /* Cache size and characteristics of multi-core processors */

== Cache size and characteristics of multi-core processors ==

The following tables shows the current tide of the multicore processors's cache.

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

=== AMD ===
{| border="1" cellspacing="0"
!Processor
!L1 Cache
!L2 Cache
!L3 Cache
!Description
|-
!Opteron Server/Workstation
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!1 MB per core, 16-way associative
!
!Dual cores, introduced on 4/22/2005
|-
!Athlon64 X2 family
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!up to 1 MB per core, 16-way associative
!
!Dual cores, intoduced on 5/13/2005
|-
!Athlon64 FX
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!up to 1 MB per core, 16-way associative
!
!High performance desktop
|-
!Turion64 X2
!Total 256KB (128K per core)
!Total 1MB (512K per core)
!
!For Laptop
|}

=== ARM ===
MPCore container for ARM9 & ARM11 High-performance embedded and entertainment

=== Broadcom ===
* SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

=== CT3600 ===
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

=== Cavium Networks ===
* Octeon
16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core

=== IBM ===
* Cell
In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

* Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

* Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M

* Power5
Dual core
L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way

* PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol

=== Intel ===
* Core2 Quad

* Xeon Quad core
12/13/2006

* Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

* Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

* Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
* Core2 Duo
Xeon (x1xx) Dual core

* Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

* Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

* Itanium 2
Multi-core
Montecito
L1:32KB
L2:256KB
L3:up to 9MB

=== PARISC ===
* PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

=== Stream Processors ===
* Strom-1 fmaily
40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction
96K VLIW instruction memory

=== Sun Microsystems ===
* UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

* UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

* UlatraSPARC T1
8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

=== AMD ===

* Athlon 64
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T23:03:18Z

Sykang: /* Cache size and characteristics of multi-core processors */

== Cache size and characteristics of multi-core processors ==

The following tables shows the current tide of the multicore processors's cache.

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

=== AMD ===
{| border="1" cellspacing="0"
!Processor
!L1 Cache
!L2 Cache
!L3 Cache
!Description
|-
!Opteron Server/Workstation
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!1 MB per core, 16-way associative
!&nbsp
!Dual cores, introduced on 4/22/2005
|-
!Athlon64 X2 family
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!up to 1 MB per core, 16-way associative
!&nbsp
!Dual cores, intoduced on 5/13/2005
|-
!Athlon64 FX
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!up to 1 MB per core, 16-way associative
!&nbsp
!High performance desktop
|-
!Turion64 X2
!Total 256KB (128K per core)
!Total 1MB (512K per core)
!&nbsp
!For Laptop
|}

=== ARM ===
MPCore container for ARM9 & ARM11 High-performance embedded and entertainment

=== Broadcom ===
* SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

=== CT3600 ===
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

=== Cavium Networks ===
* Octeon
16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core

=== IBM ===
* Cell
In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

* Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

* Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M

* Power5
Dual core
L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way

* PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol

=== Intel ===
* Core2 Quad

* Xeon Quad core
12/13/2006

* Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

* Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

* Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
* Core2 Duo
Xeon (x1xx) Dual core

* Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

* Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

* Itanium 2
Multi-core
Montecito
L1:32KB
L2:256KB
L3:up to 9MB

=== PARISC ===
* PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

=== Stream Processors ===
* Strom-1 fmaily
40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction
96K VLIW instruction memory

=== Sun Microsystems ===
* UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

* UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

* UlatraSPARC T1
8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

=== AMD ===

* Athlon 64
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T23:02:27Z

Sykang: /* AMD */

== Cache size and characteristics of multi-core processors ==

The following tables shows the current tide of the multicore processors's cache.

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

=== AMD ===
{| border="1" cellspacing="0"
!Processor
!L1 Cache
!L2 Cache
!L3 Cache
!Description
|-
!Opteron Server/Workstation
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!1 MB per core, 16-way associative
!
!Dual cores, introduced on 4/22/2005
|-
!Athlon64 X2 family
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!up to 1 MB per core, 16-way associative
!
!Dual cores, intoduced on 5/13/2005
|-
!Athlon64 FX
!64K Data + 64K Instruction per core
2-way associative data cache, two 64bits operations per cycle, 3 cycle latency
2-way associative instruction cache,
!up to 1 MB per core, 16-way associative
!
!High performance desktop
|-
!Turion64 X2
!Total 256KB (128K per core)
!Total 1MB (512K per core)
!
!For Laptop
|}

=== Broadcom ===
* SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

=== CT3600 ===
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

=== Cavium Networks ===
* Octeon
16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core

=== IBM ===
* Cell
In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

* Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

* Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M

* Power5
Dual core
L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way

* PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol

=== Intel ===
* Core2 Quad

* Xeon Quad core
12/13/2006

* Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

* Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

* Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
* Core2 Duo
Xeon (x1xx) Dual core

* Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

* Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

* Itanium 2
Multi-core
Montecito
L1:32KB
L2:256KB
L3:up to 9MB

=== PARISC ===
* PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

=== Stream Processors ===
* Strom-1 fmaily
40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction
96K VLIW instruction memory

=== Sun Microsystems ===
* UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

* UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

* UlatraSPARC T1
8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

=== AMD ===

* Athlon 64
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T22:16:49Z

Sykang: /* Cache size and characteristics of single-core processors */

== Cache size and characteristics of multi-core processors ==

The following tables shows the current tide of the multicore processors's cache.

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

=== AMD ===
* Opteron Server/Workstation
2 cores, 4/22/2005
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: 1 MB per core, 16way associative

* Athlon 64 X2 family
2 cores, 5/13/2005
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative

* Athlon 64 FX High performance desktop
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative

* Turion 64 X2 Laptop
L1: Total 256KB (128K per core)
L2: Total 1MB (512K per core)
ARM MPCore container for ARM9 & ARM11 High-performance embedded and entertainment

=== Broadcom ===
* SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

=== CT3600 ===
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

=== Cavium Networks ===
* Octeon
16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core

=== IBM ===
* Cell
In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

* Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

* Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M

* Power5
Dual core
L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way

* PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol

=== Intel ===
* Core2 Quad

* Xeon Quad core
12/13/2006

* Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

* Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

* Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
* Core2 Duo
Xeon (x1xx) Dual core

* Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

* Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

* Itanium 2
Multi-core
Montecito
L1:32KB
L2:256KB
L3:up to 9MB

=== PARISC ===
* PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

=== Stream Processors ===
* Strom-1 fmaily
40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction
96K VLIW instruction memory

=== Sun Microsystems ===
* UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

* UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

* UlatraSPARC T1
8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

=== AMD ===

* Athlon 64
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T22:16:20Z

Sykang: /* Cache size and characteristics of multi-core processors */

== Cache size and characteristics of multi-core processors ==

The following tables shows the current tide of the multicore processors's cache.

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

=== AMD ===
* Opteron Server/Workstation
2 cores, 4/22/2005
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: 1 MB per core, 16way associative

* Athlon 64 X2 family
2 cores, 5/13/2005
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative

* Athlon 64 FX High performance desktop
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative

* Turion 64 X2 Laptop
L1: Total 256KB (128K per core)
L2: Total 1MB (512K per core)
ARM MPCore container for ARM9 & ARM11 High-performance embedded and entertainment

=== Broadcom ===
* SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

* SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

=== CT3600 ===
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

=== Cavium Networks ===
* Octeon
16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core

=== IBM ===
* Cell
In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

* Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

* Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M

* Power5
Dual core
L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way

* PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol

=== Intel ===
* Core2 Quad

* Xeon Quad core
12/13/2006

* Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

* Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

* Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
* Core2 Duo
Xeon (x1xx) Dual core

* Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

* Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

* Itanium 2
Multi-core
Montecito
L1:32KB
L2:256KB
L3:up to 9MB

=== PARISC ===
* PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

=== Stream Processors ===
* Strom-1 fmaily
40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction
96K VLIW instruction memory

=== Sun Microsystems ===
* UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

* UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

* UlatraSPARC T1
8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T22:10:28Z

Sykang: /* Reference */

== Cache size and characteristics of multi-core processors ==

Wiki: Cache sizes in multicore architectures

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

AMD Opteron Server/workstation
2 cores, 4/22/2005

L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: 1 MB per core, 16way associative

Athlon 64 X2 family 2 cores
5/13/2005
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative
Athlon 64 FX High performance desktop
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative
Athlon64 ### L1: 64K Data + 64K Instr.
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2 : 512K
16 way associative
Turion 64 X2 Laptop
L1: Total 256KB (128K per core)
L2: Total 1MB (512K per core)
ARM MPCore container for ARM9 & ARM11 High-performance embedded and entertainment

Broadcom SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

CT3600
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

Cavium Networks Octeon 16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core
IBM Cell In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M
Power5 Dual core

L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way
PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol
Intel Core2 Quad
Xeon Quad core
12/13/2006

Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
Core2 Duo
Xeon (x1xx) Dual core

Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

Itanium 2 Multi-core
Montecito

Itanium2
L1:32KB
L2:256KB
L3:up to 9MB
PARISC PA8800 PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

Stream Processor Strom-1 fmaily 40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction

96K VLIW instruction memory

Sun Microsystems UltraSPARC IV
UltraSPARC IV+ UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

UlatraSPARC T1 8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

== Conclusion ==

== References ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T22:10:20Z

Sykang: /* Reference */

== Cache size and characteristics of multi-core processors ==

Wiki: Cache sizes in multicore architectures

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

AMD Opteron Server/workstation
2 cores, 4/22/2005

L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: 1 MB per core, 16way associative

Athlon 64 X2 family 2 cores
5/13/2005
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative
Athlon 64 FX High performance desktop
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative
Athlon64 ### L1: 64K Data + 64K Instr.
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2 : 512K
16 way associative
Turion 64 X2 Laptop
L1: Total 256KB (128K per core)
L2: Total 1MB (512K per core)
ARM MPCore container for ARM9 & ARM11 High-performance embedded and entertainment

Broadcom SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

CT3600
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

Cavium Networks Octeon 16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core
IBM Cell In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M
Power5 Dual core

L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way
PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol
Intel Core2 Quad
Xeon Quad core
12/13/2006

Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
Core2 Duo
Xeon (x1xx) Dual core

Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

Itanium 2 Multi-core
Montecito

Itanium2
L1:32KB
L2:256KB
L3:up to 9MB
PARISC PA8800 PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

Stream Processor Strom-1 fmaily 40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction

96K VLIW instruction memory

Sun Microsystems UltraSPARC IV
UltraSPARC IV+ UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

UlatraSPARC T1 8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

== Conclusion ==

== Reference ==
[1] http://www.amd.com/us-en/Processors/ProductInformation

[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250

[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor

[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets

[5] http://www.sun.com/processors/UltraSPARC-IV/

[6] http://www.sun.com/processors/UltraSPARC-IV+/

[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml

[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html

[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html

[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html

[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T22:10:01Z

Sykang: /* Reference */

== Cache size and characteristics of multi-core processors ==

Wiki: Cache sizes in multicore architectures

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

AMD Opteron Server/workstation
2 cores, 4/22/2005

L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: 1 MB per core, 16way associative

Athlon 64 X2 family 2 cores
5/13/2005
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative
Athlon 64 FX High performance desktop
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative
Athlon64 ### L1: 64K Data + 64K Instr.
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2 : 512K
16 way associative
Turion 64 X2 Laptop
L1: Total 256KB (128K per core)
L2: Total 1MB (512K per core)
ARM MPCore container for ARM9 & ARM11 High-performance embedded and entertainment

Broadcom SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

CT3600
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

Cavium Networks Octeon 16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core
IBM Cell In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M
Power5 Dual core

L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way
PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol
Intel Core2 Quad
Xeon Quad core
12/13/2006

Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
Core2 Duo
Xeon (x1xx) Dual core

Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

Itanium 2 Multi-core
Montecito

Itanium2
L1:32KB
L2:256KB
L3:up to 9MB
PARISC PA8800 PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

Stream Processor Strom-1 fmaily 40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction

96K VLIW instruction memory

Sun Microsystems UltraSPARC IV
UltraSPARC IV+ UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

UlatraSPARC T1 8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

== Conclusion ==

== Reference ==
[1] http://www.amd.com/us-en/Processors/ProductInformation
[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250
[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor
[4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets
[5] http://www.sun.com/processors/UltraSPARC-IV/
[6] http://www.sun.com/processors/UltraSPARC-IV+/
[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml
[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html
[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html
[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html
[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T22:08:57Z

Sykang:

== Cache size and characteristics of multi-core processors ==

Wiki: Cache sizes in multicore architectures

Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

AMD Opteron Server/workstation
2 cores, 4/22/2005

L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: 1 MB per core, 16way associative

Athlon 64 X2 family 2 cores
5/13/2005
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative
Athlon 64 FX High performance desktop
L1: 64KB (Data) + 64KB (Instruction) per core
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2: up to 1 MB per core, 16way associative
Athlon64 ### L1: 64K Data + 64K Instr.
2way associative data cache, two 64bits operations per cycle, 3 cycle latency
2way associative instruction cache,
L2 : 512K
16 way associative
Turion 64 X2 Laptop
L1: Total 256KB (128K per core)
L2: Total 1MB (512K per core)
ARM MPCore container for ARM9 & ARM11 High-performance embedded and entertainment

Broadcom SiByte SB1250
Two scalable MIPS core, MESI
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

SB1255
L1: 32K data + 32K instruction
Cache block 32 bytes
Cache line 32 bytes
L1 to L1 latency : 28~36 cycles

L2: 512K shared, ECC, 4way associative
32 bytes cache line

SB1455
L1: 32K data + 32K instruction

L2: 1MB shared, 8way associative, ECC protected
Cradle Technology CT3400
CT3600 Multi-core DSP
CT3400
8 32bits DSPs, 6 RISC-like CPUs
32K instruction cache, 64K local data memory

CT3600
2 quad DSPs, 8 DPS per quad, 32KB instruction cache per quad, 125K data memory per quad

Cavium Networks Octeon 16 MIPS cores
CN38XX/CN36XX 4 to 16 MIPS64 cores
1M ECC protected shared L2 (CN38XX), 512K (CN36XX)
32K instruction cache/8K data cache/2K write buffer per every MIPS core
IBM Cell In the PlayStation 3
PowerPC based
8 cores optimized for vector operation
Power4 1st dual core
2000

Power4
L1: 64K per CPU instruction cache(128byte line, dirrect map, LRU)
32K per CPU data cache (2way, 128byte line, LRU)
L2: 1440K, 8way, 128 byte line
L3: 128M, 8way 512 byte line

Power4+
L1: data 32K(2way set), instruction 64K(directly mapped)
L2: 3 x 0.5M shared by dual core, 40B/cycle per port
L3: 32M
Power5 Dual core

L1: I-64K(2way LRU), D-32K(4way, LRU)
L2: three 0.625M, 10way, LRU, 128 byte line
L3: 36M, 12way
PowerPC 970MP Dual
In the Apple PowerMac
L1: 32K data(2 way associative with parity protection), 64K instruction (directly mapped)

L2: 1M per core, ECC
Cache-coherency snooping protocol
Intel Core2 Quad
Xeon Quad core
12/13/2006

Xeon 5000
L1: 16KB (Data cache per core)+ 12KµOPS(Trace cache per core)
L2: 2MB per core

Xeon MP7000
L1:16KB (Data cache per core)+ 12K µOPS (Trace cache per core)
L2: 1MB per core or 2x2MB per core

Xeon MP7300
L1: 32K data per core, 32K instruction per core
L2: up tp 8MB, snoop filter, 4M shared L2 per die
Core Duo
Core2 Duo
Xeon (x1xx) Dual core

Xeon 5100
L1 : 32KB (Data) + 32KB (Instruction) per core
L2 : 4MB (Shared)

Xeon 7100
L1: 16K data
L2: 2M 8way ECC
L3: up to 16M ECC. 16way

Itanium 2 Multi-core
Montecito

Itanium2
L1:32KB
L2:256KB
L3:up to 9MB
PARISC PA8800 PA8800
L1: 1.5M data 4way set, 1.5M instruction 4way set, 2cycle
L2: 32M

Stream Processor Strom-1 fmaily 40 to 80 ALUs

SP16HP-G220, SP16-G160, SP8-G80
L1: 32K data, 16K instruction

96K VLIW instruction memory

Sun Microsystems UltraSPARC IV
UltraSPARC IV+ UltraSPARC IV
dual
L1: 64K data, 32K instruction
L2: up to 16MB, external 8M 2way set associative per core
Cache line sizes changed 512 to 128 bytes to reduce data contentionassociated with sub-blocked cache, LRU replacement policy, ECC
write cache: hash-indexed 2K,
2K prefetch cache

UltraSPARC IV+
L2: 2M on-chip
L3: 32M external

UlatraSPARC T1 8 cores
L1: 16K instruction cache per core, 4way-set associative parity protected
8K data cache , parity protected, 4way set associative

L2: 3M 12way, 4banks, ECC

== Cache size and characteristics of single-core processors ==

== Conclusion ==

== Reference ==
http://www.amd.com/us-en/Processors/ProductInformation
http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250
http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor
http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets
http://www.sun.com/processors/UltraSPARC-IV/
http://www.sun.com/processors/UltraSPARC-IV+/
http://www.sun.com/processors/UltraSPARC-T1/specs.xml
http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html
http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html
http://www.netlib.org/utk/papers/advanced-computers/power4.html
http://www.netlib.org/utk/papers/advanced-computers/power5.html

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T22:03:32Z

Sykang: /* Cache size and characteristics of multi-core processors */

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T21:53:54Z

Sykang: /* Cache size and characteristics of multi-core processors */

== Cache size and characteristics of multi-core processors ==

== Cache size and characteristics of single-core processors ==

== Conclusion ==

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T21:53:07Z

Sykang: /* Cache size and characteristics of multi-core processors */

== Cache size and characteristics of multi-core processors ==

CSC/ECE 506 Fall 2007/wiki2-5-as

2007-09-24T21:50:36Z

Sykang: CSC/ECE 506 Fall 2007/wiki2-5-as moved to CSC/ECE 506 Fall 2007/wiki2 5 as: To match with the naming rule

#REDIRECT [[CSC/ECE 506 Fall 2007/wiki2 5 as]]

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T21:50:36Z

Sykang: CSC/ECE 506 Fall 2007/wiki2-5-as moved to CSC/ECE 506 Fall 2007/wiki2 5 as: To match with the naming rule

= Cache size and characteristics of multi-core processors =

CSC/ECE 506 Fall 2007/wiki2 5 as

2007-09-24T21:48:25Z

Sykang:

= Cache size and characteristics of multi-core processors =

Talk:CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:36:31Z

Sykang:

= The reviewer pointed out as below.

"not very well; a separate section for superscalar could have been added rather than clubbing it with VLIW"

It seems to be persuadable, however, I don't think so because superscalar processor has been the most major issues over most micro architecure past 20 years more. The explored architecure such as VLIW and others by this assignment are based on basically supersclar processor, although superscalar is the most important architecture. The visited architectures are a kind of additional benecial features on superscalar.

= The reviewer pointed out the material seems not to be original, because the rephrased paragraph took small portion. The updated version are restructured, rephrased and added version of the previous one.

= The reviewer pointed out as below.

"the author mentions that the current technology used in .13 microns. I think the current market trend is .045 microns with active research going on on .022 micron technology. That fact could have been mentioned."

There were misunderstood of length unit, micron. The new version reflects new information.

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:28:04Z

Sykang: /* Architectural Trends */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has total of 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors are attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg]]

it takes 14 cycles for loop body.

If VLIW instructions are used, then

[[Image:VLIW.jpg]]

it takes 9 cycles assuming 5 execution pipelines.

MIPS R10000 is also a good example. It has 2 integer functional units and 3 types of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Yet another example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread quickly.

For attaining multi-threading, there are two basic approaches; fine-grained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instructions from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with a high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has the cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading that uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Figure 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good examples of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, more than just accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[12]

[[Image:speculative.jpg]]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as does checkpoint. While checkpointing, the processor duplicates the copy of information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaims the stored information for use by new predicted branches. But if the prediction is incorrect, it resotres the execution information from the corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, and AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).

[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.

----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

[12] Eric Rotenberg, ECE721 Advanced Microarchitecture lecture notes, NCSU, 2007

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:10:02Z

Sykang: /* Speculative Execution */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[12]

[[Image:speculative.jpg]]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).

[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.

----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

[12] Eric Rotenberg, ECE721 Advanced Microarchitecture lecture notes, NCSU, 2007

File:Speculative.jpg

2007-09-11T02:09:47Z

Sykang:

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:09:39Z

Sykang: /* Speculative Execution */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[12]

[[Image:speculative.jpg]]
Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).

[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.

----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

[12] Eric Rotenberg, ECE721 Advanced Microarchitecture lecture notes, NCSU, 2007

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:07:01Z

Sykang: /* References */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).

[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.

----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

[12] Eric Rotenberg, ECE721 Advanced Microarchitecture lecture notes, NCSU, 2007

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:03:19Z

Sykang: /* Updated Figure 1.8 & 1.9 */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).

[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.

----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:02:19Z

Sykang: /* VLIW */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).
[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.
----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:01:57Z

Sykang: /* VLIW */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg|left]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg|left]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg|left]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).
[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.
----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:01:37Z

Sykang: /* VLIW */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg|left]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg|left]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg|left]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).
[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.
----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:01:02Z

Sykang: /* VLIW */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg|left]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg|left]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg|left]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).
[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.
----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:00:39Z

Sykang: /* VLIW */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg|left]]~

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg|left]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg|left]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).
[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.
----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T02:00:02Z

Sykang: /* VLIW */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:

[[Image:simpleMIPS.jpg|left]]

If loop-unrolling and scheduling the code are applied, then

[[Image:loopunrollMIPS.jpg|left]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg|left]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).
[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.
----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T01:59:16Z

Sykang: /* VLIW */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:
[[Image:simpleMIPS.jpg|left]]

If loop-unrolling and scheduling the code are applied, then
[[Image:loopunrollMIPS.jpg|left]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg|left]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).
[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.
----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html

CSC/ECE 506 Fall 2007/wiki1 4 a1

2007-09-11T01:58:53Z

Sykang: /* VLIW */

== Architectural Trends ==
[[Image:MIPSR10000.jpg|thumb|right|300px|Fig.1 MIPS R10000 Block Diagram (From Fig. 2 of [3])]]
[[Image:IntelMoorsLaw.jpg|thumb|right|300px|Fig.2 The number of trnasistors on a chip of Intel]]
Feature size means the minimum size of transistors or a wire width which are used for connectiong transistors and other circuit components. Feature sizes have dramatically decreased from 10 microns in 1971 to 0.18 microns in 2001. These advanced integrated circuit processes allowed the integration of one billion transistors on a single chip and enabled more complicated and faster microprocessor architecure which have evolved to the direction of increasing parallelism; [http://en.wikipedia.org/wiki/Instruction_level_parallelism ILP] and [http://en.wikipedia.org/wiki/Thread_level_parallelism TLP]. With respect to microprocessor architecture, as superscalar processor prevails, several additional exploitable architectures were also proposed during past 10 years as other past decades did. Based on superscalar architecture, VLIW, superspeculative, simultaneous multithreading, chip multiprocessor and so on were proposed and explored. These techniques tried to overcome the control and data hazard as deep pipelining and multiple issue overwhelms as well as to maximize the throughput of computing by TLP.

For example, MIPS R10000 is a superscalar processor executed by out of order manner, which has 6.8 million transistors on 16.64mm x 17.934 mm(298mm^2) dimension using 0.35um process. It fetches 4 instructions simultaneously and has totally 6 pipelines; 5 pipe lines for execution and 1 pipe line for fetching and decoding. Each execution pipelines can be categorized into 3 kinds of execution - integer, float and load/store.

----

=== VLIW ===
VLIW(Very Long Instruction Word) is one way to expedite ILP under multiple-issue processors. Multiple-issue processors can be attainable by two basics - superscalar and VLIW. The big difference between superscalar and VLIW is located on the scheduling method of instructions. Whlie superscalar processors issue multiple numbers of instructions per clock, which are scheduled either statically or dynamically, VLIWs issue statically sceduled instructions by the compiler. Both superscalar and VLIW have multiple and independent functional units.

VLIW processor's compiler analyzes the programmer's instructions and then groups multiple independent instructions into a large packaged instruction. VLIW issues a fixed number of instructions, the format of which can be either one large instruction or a fixed instruction packet with the parallelism.

To look into the inside of VLIW operation, assume the below example code for MIPS[1].

for (i=1000; i>0; i=i-1) x[i] = x[i] + s;

The standard MIPS code looks like this:
[[Image:simpleMIPS.jpg|left]]

If loop-unrolling and scheduling the code are applied, then
[[Image:loopunrollMIPS.jpg|left]]

It takes 14 cycles for loop body.

If VLIW instructions are used, then
[[Image:VLIW.jpg|left]]

MIPS R10000 is also example. it has 2 integer functional units and 3 kinds of operands. Hence, the compiler can generate one instruction which contains 3 integer operations with the corresponding operands to each operation. Other example of VLIW is i860 of Trimedia.

----

=== Multi-threading ===
[[Image:SMTEx.jpg|thumb|right|300px|Fig.3 Four different approaches of using issue slots in superscalar processor (Redrawn from Fig 6.44 of [1])]]
Multi-threading enables exploiting thread-level parallelism(TLP) within a single processor. It allows multiple threads to share the functional units of a single processor by an overlapping manner. For this sharing, the processor has to maintain the duplicated state information of each thread-register file, PC, page table and so on. In addition, the processor can switch the different thread enough quickly.

For attaining multi-threading, there are two basic approaches; fine-garained multi-threading and coarse-grained multi-threading. The former switches each instruction between multiple interleaved threads. For this interleaving, the processor can switch threads on every clock cycle. The advantage of this architecture can prohibit stalling, because other instruction from other threads can be performed when one thread stalls. The disadvantage makes slow down the individual thread's execution, because even though the instruction is ready to be executed, it can be interleaved by another thread's instruction.

The latter switches threads when it meets the stall only with high cost. This policy reduces unnecessary switching of thread, so that the individual thread does not need to slow down its execution contrary to the fine-grained case. However, it has a cost when switching occurs to fill the pipeline. This kind of processor issues instructions from a single thread, although it switches the running thread. If the stall occurs, the pipeline is empty. Then, in order to execute a new thread instead of stalled thread, the pipeline has to be filled, which results in the cost.

The Simultaneous multithreading (SMT) is a kind of multithreading which uses the resources of a multiple-issue, dynamically scheduled processor to exploit TLP. At the same time it exploits ILP using the issue slots in a single clock cycle. Fig. 3 shows the comparison between three kinds of multi-threading in addition to a superscalar processor.

----

=== Multi-core ===
[[Image:Smithfield_die_med.jpg|thumb|right|80px|Fig.4 Intel® Pentium® processor Extreme Edition processor die [7]]]
Multi-core CPUs have multiple numbers of CPU cores on a single die. They are connected to each other through a shared L2 or L3 cache, or a glue logic like switch and bus on a die. Every CPU core on a die shares interconnect components with which to interface to other processors and the rest of the system. These components include a FSB (Front Side Bus), a memory controller, a cache coherent link to other processors, and a non-coherent link to the southbridge and I/O devices. The advantages of multi-core chips are power-efficiency and simplicity around the processors. Since multiple processors are packed into a single die, the glue logics which are required to connect to each processor are also packed into a die. It saves power and simplifies auxilary circuits than coupled processors, which need PCB circuits.
Intel Pentium Extreme, Coreduo and Coreduo2 are good example of multi-core processors.
Intel Xeon X7300 series has quad-core in a single die with 65nm processing.

----

=== Speculative Execution ===
While trying to get more ILP, managing control dependencies becomes more important but more burden. To reduce the cost of stall because of branch, branch prediction techinque is applied for the instruction fetching stage. However, for the processor which executes multiple instructions per clock, More things than accurate prediction are required. To speculate is to act on these predictions; fetch and execute instructions from the predicted path.[]

Under speculative execution, fetch, issue, and execute instructions are performed as if branch predictions were always correct. When misprediction occurs, the recovery mechanism handles this situation. If the processor meets a branch, it predicts the branch target and follows that path as well as checkpoint. While checkpointing, the processor duplicates the copy information such as register files and control information and another possible branch target and so on. If the prediction is correct, the processor reclaim the stored information for use by new predicated branches. But if the prediction is incorrect, it resotres the execution information from corresponding checkpoint. There are examples like PowerPC 603/604/G3/G4, MIPS R10000/R12000, Intel Pentium II/III/4, Alpha 21264, AMD K5/K6/Athlon.

----

== Updated Figure 1.8 & 1.9 ==
[[Image:fig18.jpg|frame|Figure 1.8 Number of processors in fully configured commercial bus-based shared memory multiprocessors]]

Figure 1.8 of our book has been updated to incorporate trends from 2000 to the present. SGI Origin 3000 series were reintroduced as Origin 3400 and Origin 3900 in year 2000 and 2003, respectively. Sun introduced even more powerful enterprise servers than E10000, which are E15000 in year 2002, E20000 and E25000 in year 2006. HP's high-end supercomputer 9000 Superdome with 16, 32, and 64 processors are released this year(2007).
[[Image:fig19.jpg|frame|Figure 1.9 Bandwidth of the shared memory bus in commercial multiprocessors(Y-axis is log-scaled)]]

Figure 1.9 shows the bandwidth of shared memory bus of those servers introduced in figure 1.8, which are SGI Origin 3000 series, SUN Enterprise 15K, 20K, and 25K as well as IBM p5 590 and HP9000 Superdome. In the case of Sun E25K, the bandwidth available is 43.2 GBps and the aggregated bandwith exceeds 100GBps. Origin 3900 has 12.8 GBps bandwidth and the aggregate bandwidth of 172.8 GBps.
----

== References ==
[1] John L. Hennessy, David A. Patterson, "Computer Architecture: A Quantitative Approach" 3rd Ed., Morgan Kaufmann, CA, USA

[2] CE Kozyrakis, DA Patterson, "A new direction for computer architecture research",
Computer Volume 31 Issue 11, IEEE, Nov 1998, pp24-32

[3] K.C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro Volume 16 Issue 2, Apr. 1996, pp28-41

[4] Geoff Koch, "Discovering Multi-Core: Extending the Benefits of Moore’s Law", Technology@Intel Magazine, Jul 2005, pp1-6

[5] Richard Low, "Microprocessor trends:multicore, memory, and power developments", Embedded Computing Design, Sep 2005

[6] Artur Klauser, "Trends in High-Performance Microprocessor Design", Telematik 1, 2001

[7] http://www.intel.com & http://www.intel.com/pressroom/kits/pentiumee

[8] http://www.alimartech.com/9000_servers.htm

[9] http://www.sun.com/servers/index.jsp?gr0=cpu&fl0=cpu4&gr1=

[10] http://www.sgi.com/pdfs/3867.pdf

[11] http://www-03.ibm.com/systems/p/hardware/highend/590/index.html