https://wiki.expertiza.ncsu.edu/api.php?action=feedcontributions&feedformat=atom&user=MbplautzExpertiza_Wiki - User contributions [en]2026-08-20T23:46:22ZUser contributionsMediaWiki 1.41.0https://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/10a_vm&diff=61630CSC/ECE 506 Spring 2012/10a vm2012-04-07T03:07:01Z<p>Mbplautz: Section VI</p>
<hr />
<div>Prefetching and consistency models.<br />
== Prefetching ==<br />
<br />
=== Introduction to prefetching ===<br />
<br />
Almost all processors today use [http://en.wikipedia.org/wiki/Instruction_prefetch prefetching] as a means to speed up execution. Primarily, prefetching is used to shorten the amount of time a processor is in the wait state by predicting which cache block would be accessed next, so that when a [http://en.wikipedia.org/wiki/CPU_cache#Cache_miss cache miss] occurs, the old block in the cache can be immediately replaced with the block that is prefetched and hence decreasing the idle time of the processor. Performance in prefetching is best when it is done by following the [http://en.wikipedia.org/wiki/Out-of-order_execution program order]. However, it need not always be that prefetching is done in program order; a processor trying to guess the result of a calculation during a complex [http://en.wikipedia.org/wiki/Branch_prediction branch prediction] algorithm will need to anticipate the result and fetch the right set of instructions for execution. Things get more complex when it comes to graphical processing units or GPUs. Prefetching can take advantage of [http://en.wikipedia.org/wiki/Coherence_(physics)#Spatial_coherence spatial coherence] and the data that is prefetched are not a set of instructions, but instead they are texture elements that can be mapped to a polygon.<ref>[http://en.wikipedia.org/wiki/Instruction_prefetch Instruction prefetch wiki article.]</ref><br />
<br />
=== Types of prefetching ===<br />
<br />
[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] can be primarily classified based on whether it is binding or non-binding, and whether it is hardware or software controlled. Using a binding prefetch, the value of a later reference, like a register load, is bound at the time the prefetch completes. However, this comes with added restrictions because the value in the prefetch might not be accurate - there might be invalidations that can be caused by another processor in the time frame between prefetch and reference by the current processor. Coming to the non-binding prefetch case, the data is stored into the processor cache, and the coherence is maintained till the processor reads or writes the value. This approach, unlike binding prefetch, will not have an effect on the correctness of any consistency model. It can serve as a serious improvement in terms of performance.<br />
<br />
The prefetch that is interesting to us is the hardware controlled and non-binding prefetch. Prefetching done in software involves significant effort from the programmer's side, and it may not be scalable as the length of the program increases. In comparison, the non-binding prefetch yields significantly more performance when compared to the binding prefetch. The major performance enhancement from prefetching comes by decreasing the memory latencies that are caused by all consistency models. <br />
<br />
In the case of a read operation, the read prefetch is issued to get the data in a read-only shared state in the cache. Since we are considering the non-binding prefetch, there is a guarantee that the read operation is going to return a correct value when it is allowed to run, irrespective of the actual prefetch completion time. However, there is also a catch to this: the value read might not always be correct. Consider a case where there is a write operation performed on the memory location that was just read-prefetched. Thus the value can be read again depending on whether an invalidation-based or an update-based coherence scheme is being used. If an [http://en.wikipedia.org/wiki/Cache_coherence update-based coherence scheme] is being used, we can be assured that the other processor will send a bus update and the current processor can pick it up to update its value. However, if an invalidation based coherence scheme is used, there would be a coherence miss and the value will be read again from the system memory, giving an illusion that the prefetch did not occur.<br />
<br />
In the case of a write operation, to acquire the exclusive ownership of the line, a read-exclusive prefetch can be used. Since it is cached in the exclusive mode, a write operation can proceed without incurring an invalidate or an update on other caches which have cached the same line or block. The write operation finishes quickly because the value is already cached and there is no coherence miss, thus reducing the idle time of the processor. However, it is to be noted that the read-exclusive prefetch is only possible if the coherence scheme is invalidation-based and not update-based. The same logic of incorrectness applies here that we have seen in the read case: suppose that another processor asks for a write to the same block; in this case, the exclusive ownership will no longer be maintained. Instead the cache block will be invalidated.<br />
<br />
=== How does prefetching work ? ===<br />
<br />
In a multiprocessor environment, each processor has a [http://en.wikipedia.org/wiki/Memory_disambiguation load] and a [http://en.wikipedia.org/wiki/Memory_disambiguation store buffer]. The way in which consistency models work are that the accesses to memory locations are delayed until the previous requests have finished. While issuing a read or a write request, we can implement the prefetch by making the hardware automatically issue a prefetch for requests which are in the load or store buffer and those requests which cannot be honored right away because of the delays incurred due to consistency model constraints. <br />
<br />
Let us trace through the steps a prefetch request would follow. First, it looks up the cache to see whether the block is already present. If it is indeed available, the request is terminated. If it is not present, the prefetch is issued to memory. Depending on the type of prefetch technique we are using, the response to the prefetch may or may not be immediate. The response is then placed in the cache. This process can be optimized by detecting duplicate requests to the same location and then combining the responses to each individual request to point to the prefetch request, thereby preventing duplicate requests being issued to memory. This mechanism also taxes the system in the form of requirements. Firstly, it requires that hardware coherent caches and the block that is prefetched should fit into the cache. Then for the write prefetch to work efficiently, there should be an invalidation-based coherence scheme in place. Additionally, the bus bandwidth should be high in order to handle several prefetch requests at the same time. The caches will also be more busy with read/write transactions when prefetching is implemented.<ref>[http://www.opensparc.net/pubs/papers/InstrPfHPCA05.pdf Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications]</ref> <br />
<br />
The amount of lookahead we do for a prefetch needs to be controlled, in the sense that if a higher number of blocks are prefetched than are required, then the processor might not ever use them and it would also result in increased cache misses of actually required blocks. Thus the extent to which lookahead is done should dynamically adjust depending on whether the processor actually uses the blocks or just evicts them without a read or a write reference to it.<br />
<br />
== Prefetching with Sequential Consistency ==<br />
<br />
Sequential Consistency (SC) might cause a reader to assume that its implementation will need a single memory module. However, this is not true. Both SC and the relaxed memory models allow many optimizations within them in order to deliver high performance. SC and the relaxed models allow non-binding prefetching along with coherent caching.<ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&sqi=2&ved=0CCkQFjAA&url=ftp%3A%2F%2Fftp.cs.wisc.edu%2Fpub%2Ftechreports%2F1991%2FTR1006.pdf&ei=cZ57T-j7DNCbtwenqIG1CA&usg=AFQjCNHtHiuYi2hYaVbTkSuELNg7PNQuXA&sig2=VFMR7Hq3ofiDnH8tzbFNUg Cache consistency and sequential consistency]</ref><br />
<br />
'''Let us take a look at an example and see how SC vs prefetching with SC performs'''<br />
<br />
The assumptions being made are that the processor has non-blocking reads with branch prediction machinery, an invalidation-based cache coherence scheme is in place, if there is a cache hit the latency is 1 clock cycle, and the cache miss incurs a latency of 100 clock cycles. <br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Since we are considering a system with SC, we know that an access to memory cannot be issued until the previous access has completed. The first three accesses are misses and they occur one after the other without any interleaving, which gives us a total latency of 100 x 3 = 300 clock cycles. The fourth operation however is a cache hit, thus adding only 1 clock cycle. The four accesses take up 301 clock cycles to complete.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance. Since the system has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
Comparing the 103 clock cycles in prefetching under SC .vs. SC only we see that there is nearly a 200 clock cycle difference, which is a significant improvement. As the number of accesses increase, the difference is only going to get larger until a certain point where "SC only" would no longer be a viable option.<br />
<br />
'''Another example showing how SC vs prefetching with SC performs'''<br />
<br />
The same assumptions are being made which we made for the first example.<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under SC only we see that the total number of clock cycles are 302.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching, we see that the total time taken will be 203 (2 misses & 3 hits).<br />
<br />
Thus again, we see that prefetching with SC performs better than "SC only".<br />
<br />
== Performance of prefetching with SC and why the idea has not been widely adopted ==<br />
<br />
We have seen two examples where prefetching with SC does a better job than "SC only". However, what we need to look at is whether this is the maximum performance which we can extract. Consider the second example where we had 3 reads in a critical section. The address which E[D] is trying to access will depend on the value of D. Read D was a cache hit, and E[D] is not allowed to perform under SC until the read C finishes. Thus, even though prefetching increases performance by reducing the time delay caused due to consistency constraints, it does not deal with situations where out of order usage of the values returned by memory access is critical for the processor to proceed efficiently. In other words, prefetching fails to do a good job when out of order consumption of values is important.<ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 Memory access dependencies in shared-memory multiprocessors]</ref><ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CDIQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.52.9935%26rep%3Drep1%26type%3Dpdf&ei=wp17T_vaKsrEtwe9yvSpCA&usg=AFQjCNGQXk84yrSUHkZU-mDw0D8KMVb6WQ&sig2=rhKqMuWKvTBHdFgK3rOthw Performance evaluation of memory consistency models for shared-memory multiprocessors]</ref><br />
<br />
Even though the main use of prefetching is to enable servicing of the requests faster when compared to the delay constraints imposed by the memory contraint models, correctness needs to be maintained at all times. The number of times a prefetched value is incorrect should be small, and luckily this is indeed true in real world systems for several reasons. The invalidation of the prefetched values is loosely coupled with the delay to obtain a correct execution sequence. These delays are imposed by the memory consistency models, and in SC, which is the strictest of all models, many delays are imposed. Usually, the time when one process releases a synchronization is much earlier when compared another process trying to acquire it. Thus the delays introduced by SC are unnecessary and therefore it taxes the systems performance. <ref>[http://dl.acm.org/citation.cfm?id=285991 Memory access buffering in multiprocessors]</ref><br />
<br />
Such cases are not rare to find in real applications and hence prefetching cannot be used all the time. Therefore, prefetching under SC was not widely adopted and hence new schemes had to be developed in order to overcome the drawbacks of the current method.<br />
<br />
== Solution#1 Prefetching with Release Consistency ==<br />
<br />
Prefetching under release consistency (RC) does at least as good as prefetching under SC. Let us evaluate its performance in the two examples we looked at previously. We follow the same assumptions about the system which we have followed previously.<br />
<br />
'''The first example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Since we are considering a system with RC, we know that write accesses to memory are delayed until the lock access can be performed. The lock L operation takes 100 clock cycles to finish, followed by another 100+1 cycles for write A, write B to finish and then finally the fourth operation takes 1 clock cycle to finish because it is a hit. Thus the total number of clock cycles are 202 under the "RC only" approach.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we can get significant improvement in terms of performance, at least compared to SC. Since the system now has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
In this example, we found that prefetching with SC and prefetching with RC take the amount of time.<br />
<br />
'''The second example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under "RC only" we can see that the total number of clock cycles are 203.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we see that the total time taken will be 202 (2 misses & 2 hits pipelined).<br />
<br />
Thus again, we see that prefetching with RC performs better than "RC only".<br />
<br />
However, we have not got a significant performance gain in the second example. Thus even though RC allows more relaxation on the order of operations issued to memory, the gain is not much. Relaxed models offer more options on the hardware implementation perspective than SC, so we might get tempted to conclude that hardware must use the relaxed models instead of SC. On the other hand, the performance gain we expect to get is not being delivered under prefetching with RC, thus it cannot be justified to be a good approach either, even though it performs better than prefetching under SC.<br />
<br />
Also, the same argument that we used for SC by mentioning that it taxes the system by causing unwanted delays to ensure correctness can be applied to the RC model as well. Though unlike SC, it may not tax the system's performance much, because in RC the delays are only inserted at synchronization points. Even then it forms a part of the argument that prefetching under RC is not a very good method.<br />
<br />
== Solution#2 Speculative Execution ==<br />
<br />
Speculative execution does impose many constraints which relaxed and SC implementations do, but rather it allows them to be more aggressive. Speculative execution allows the processor to execute instructions eagerly. However, the same strictness applies when it comes to being correct. That is, the instructions must be undone when speculations prove incorrect. This scenario can be found in wrongly predicted branches. When the processor knows that it cannot be wrong, it does a commit of the instruction, which frees up the resources that were being used for implementation. There are two strict rules about instructions being committed: <ref>[http://en.wikipedia.org/wiki/Speculative_execution Speculative Execution wiki article]</ref><br />
<br />
- All instructions prior to the current instruction must be committed, &<br />
- The current instruction operation commits.<br />
<br />
For example, when we consider a load or store operation, we can be assured that it commits when it does a read or a write on a memory value. With speculative execution, both relaxed and SC implementations can perform operations out-of-order and in a speculative fashion. Consider the comparison of the peer performance of relaxed .vs. SC:<br />
<br />
read A (miss)<br />
read B (hit)<br />
<br />
When dealing with SC, read A occurs first, gets committed and then read B gets committed. However, with relaxed models, read B can get committed before read A gets committed. The difference in performance between relaxed and SC is very narrow. However, the measurement of the difference in performance depends upon benchmarks, latencies, etc.<br />
<br />
The figure below shows an example implementation of a SE system.<ref>[http://www.csl.cornell.edu/courses/ee572/gharachorloo.icpp91.pdf Two Techniques to Enhance the Performance of Memory Consistency Models by Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]</ref><br />
<br />
[[File:SE_implementation.png|600px|Example implementation of a SE system. Source: Two Techniques to Enhance the Performance of Memory Consistency Models by<br />
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]]<br />
<br />
=== Idea behind speculative execution ===<br />
<br />
The core idea which forms the crux of speculative execution is simple and easy to understand. For example, let us consider there are two accesses a and b in the program order. a is considered to have a large latency whereas b is simply a load access. Also, the consistency model needs a to complete before b can finish. The speculative execution for load accesses proceeds as follows. The processor obtains the value returned by access b before a can complete and it proceeds. Now when a completes, the processor checks to see if the speculated return value of b before the completion of a is same as the actual value obtained after a completes. If they both match then the speculation was correct and the processor proceeds without any undo of instructions. However, if the values do not match then we need to redo access b to get the correct value <ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDUQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.57.1560%26rep%3Drep1%26type%3Dpdf&ei=lbB8T8DZKtKCtgeJ7v3mDA&usg=AFQjCNElr6qsvxH41INvR6tY12S4mDwLeQ&sig2=dk_gxOC4J7VEPz3I5EOgXA Speculative Execution in Real-Time Systems]</ref>. These steps in speculative execution can be summarized by 3 different mechanisms. Namely,<br />
<br />
a) The speculative mechanism<br />
b) The detection mechanism<br />
c) The correction mechanism<br />
<br />
'''a) The speculative mechanism -''' In the speculative mechanism, the most appropriate thing to do would be to perform the access, get the returned value and proceed to use the returned value. If there is a cache hit, the value will be returned instantly, otherwise if it is a miss the access is pipelined with other accesses just like we have seen in prefetching.<br />
<br />
'''b) The detection mechanism -''' The way to detect if the speculated value is correct or not is by redoing the access after the consistency model would have actually allowed it do be done without speculation. This however might not be the only way. If we could monitor the coherence transactions on that particular location in the cache to see if there is an invalidation, then the detection process can be faster. Thus another improvement when compared to the prefetch technique is that, in speculative execution, the cache is only accessed once unlike twice, which is the norm in prefetch technique. Going back to our example of two accesses a and b, the consistency model requires that access b is deferred until access a is complete. However, under the speculative execution, b can proceed without waiting for a to complete. The detection mechanism works by monitoring whether there is an update or invalidation at location b, which is an indication that the speculation is incorrect. However, if there are no update or invalidation messages, we can be assured that the speculated value was correct.<br />
<br />
'''c) The correction mechanism -''' Once the detection mechanism determines that the speculated value is incorrect, the correction mechanism comes into play. The first step that the correction mechanism does is that it discards the computation of the speculated value. The load accesses and the computations after the speculated value can be discarded too, just like the correction mechanism used in processors when there is a branch prediction that has gone wrong.<br />
<br />
The figure below, shows the organization of a load/store functional unit of a SE system.<br />
<br />
[[File:Load_store.png|600px|Organization of a load store functional unit]]<br />
<br />
The speculative mechanism is superior to the prefetch mechanism (both under SC and RC) by giving an opportunity to use out of order speculated values.<br />
<br />
'''Referring back to the example we discussed while talking about performance of prefetching with RC/SC'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
The pipelining in both prefetching and speculative execution will be same and thus we might expect the same level of performance. But in this case, read D does not cause a bottle neck because under speculative execution; its value can be immediately consumed before the previous accesses commit. Thus we expect both the SC and RC implementations to finish in 104 clock cycles (analogous to 4 hits and 1 miss).<br />
<br />
As soon as we know the address for the access, the load access can be issued under speculative execution irrespective of the consistency model that is being supported. Even speculative execution will impose requirements on the system. For all the three mechanisms discussed, we expect hardware support, else we might not get the performance gain that we expect if we implement the same in software.<ref>[http://impact.crhc.illinois.edu/ftp/conference/micro-93-suppression.pdf Speculative Execution Exception Recovery using Write-back Suppression]</ref><br />
<br />
=== Illustrative example ===<br />
<br />
This is the example which we will be taking up for discussion to see how SE works:<br />
<br />
[[File:SE_example.png|600px|Organization of a load store functional unit]]<br />
<br />
In the above figure, the contents of various buffers are showed along with the cache content for each event that occurs. All three mechanisms which we have discussed will be traced in the example. The reorder buffer holds the instructions that are fetched and decoded. Tracing through the set of events, initially the loads and prefetches (exclusive mode) are issued for the corresponding stores. In the meantime, while the store buffer is working on the store operations, the speculative load buffer has three loads. The returned value of read D has already been used by the processor. The second event indicates an ownership for B, however it is not immediately completed. Its completion has been reordered and delayed by the reorder buffer. The third event indicates that the value of A arrives and the entries for A are purged from both the speculative-load and reorder buffers. Once the load A completes, the reorder buffer signals the store buffer to allow the store B to complete, and this is a hit because the value is already cached and thus finishes quickly. Store C is next to be served in the reorder buffer and its access is merged with the previous prefetch request for the same location.<ref>[http://www.cs.waikato.ac.nz/timewarp/wengine/papers/gc99_1/ Data and Control Speculative Execution]</ref><br />
<br />
Now to make things interesting, let us assume that there is an invalidation for D. This would cause a mismatch in the value speculated for D and hence the load D and the instructions following it are purged, indicated by event 5. The 6th event shows the correction mechanism by fetching the two instructions again and yet again load D will be a speculative event because store C has not finished. The 7th event shows new value in location D and since it is cached and its value known, E[D] proceeds. The 8th event shows that store C has finished, and since it does not affect D, the speculative value is correct and and is retired from the reorder and speculative-load buffers. The last event signifies the completion of E[D].<br />
<br />
== Future directions and ambitious implementations ==<br />
<br />
The paper by Adve and Hill <ref>[ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.pdf Implementing Sequential Consistency In Cache-Based Systems]</ref> proposes an implementation for sequential consistency that is more efficient than conventional implementations. Their scheme requires an invalidation-based cache coherence protocol. At points where a conventional implementation stalls for the full latency of pending writes, their implementation stalls only until ownership is gained. To make the implementation satisfy sequential consistency, the new value written is not made visible to other processors until all previous writes by this processor have completed. The gains from this are expected to be limited, however, since the latency of obtaining ownership is often only slightly smaller than the latency for the write to complete. In addition, the proposed scheme has no provision for hiding the latency of read accesses. Since the visibility-control mechanism reduces the stall time for writes only slightly and does not affect the stall time for reads, its performance wont be much better than conventional implementations. In contrast, the prefetch and speculative load techniques provide much greater opportunity for buffering and pipelining of read and write accesses.<br />
<br />
The paper by Stenstrom <ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 A latency-hiding scheme for multiprocessors with buffered multistage networks]</ref> proposes a mechanism for guaranteeing access order at the memory instead of at the processor. Each request contains a processor identification and a sequence number. Consecutive requests from the same processor get consecutive sequence numbers. Each memory module has access to a common data structure called next sequence-number table (NST). The NST contains P entries, one entry per processor. Each entry contains the sequence number of the next request to be performed by the corresponding processor. This allows the mechanism to guarantee that accesses from each processor are kept in program order. Theoretically, this scheme can enhance the performance of sequential consistency. However, the major disadvantage is that caches are not allowed. This can severely hinder the performance when compared to implementations that allow shared locations to be cached.<br />
<br />
To gain significant improvement in terms of performance, there have been a number of memory consistency models proposed. One disadvantage of the relaxed memory consistency models is that they present a more complex programming model to the user. The cost of this added performance benefit, however, is the extra hardware complexity that comes with it. The prefetch technique is simple and can easily be absorbed into the modern multiprocessor architectures while the speculative execution technique is not that easy when compared to the prefetch technique. Things get more complicated when the speculative execution technique is to be incorporated into multiprocessor systems when compared to uniprocessor systems. In the future, we might expect better implementations of the speculative execution technique which will make this transition easy.<br />
<br />
== References ==<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/10a_vm&diff=61629CSC/ECE 506 Spring 2012/10a vm2012-04-07T03:03:31Z<p>Mbplautz: Section V-0,1,2</p>
<hr />
<div>Prefetching and consistency models.<br />
== Prefetching ==<br />
<br />
=== Introduction to prefetching ===<br />
<br />
Almost all processors today use [http://en.wikipedia.org/wiki/Instruction_prefetch prefetching] as a means to speed up execution. Primarily, prefetching is used to shorten the amount of time a processor is in the wait state by predicting which cache block would be accessed next, so that when a [http://en.wikipedia.org/wiki/CPU_cache#Cache_miss cache miss] occurs, the old block in the cache can be immediately replaced with the block that is prefetched and hence decreasing the idle time of the processor. Performance in prefetching is best when it is done by following the [http://en.wikipedia.org/wiki/Out-of-order_execution program order]. However, it need not always be that prefetching is done in program order; a processor trying to guess the result of a calculation during a complex [http://en.wikipedia.org/wiki/Branch_prediction branch prediction] algorithm will need to anticipate the result and fetch the right set of instructions for execution. Things get more complex when it comes to graphical processing units or GPUs. Prefetching can take advantage of [http://en.wikipedia.org/wiki/Coherence_(physics)#Spatial_coherence spatial coherence] and the data that is prefetched are not a set of instructions, but instead they are texture elements that can be mapped to a polygon.<ref>[http://en.wikipedia.org/wiki/Instruction_prefetch Instruction prefetch wiki article.]</ref><br />
<br />
=== Types of prefetching ===<br />
<br />
[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] can be primarily classified based on whether it is binding or non-binding, and whether it is hardware or software controlled. Using a binding prefetch, the value of a later reference, like a register load, is bound at the time the prefetch completes. However, this comes with added restrictions because the value in the prefetch might not be accurate - there might be invalidations that can be caused by another processor in the time frame between prefetch and reference by the current processor. Coming to the non-binding prefetch case, the data is stored into the processor cache, and the coherence is maintained till the processor reads or writes the value. This approach, unlike binding prefetch, will not have an effect on the correctness of any consistency model. It can serve as a serious improvement in terms of performance.<br />
<br />
The prefetch that is interesting to us is the hardware controlled and non-binding prefetch. Prefetching done in software involves significant effort from the programmer's side, and it may not be scalable as the length of the program increases. In comparison, the non-binding prefetch yields significantly more performance when compared to the binding prefetch. The major performance enhancement from prefetching comes by decreasing the memory latencies that are caused by all consistency models. <br />
<br />
In the case of a read operation, the read prefetch is issued to get the data in a read-only shared state in the cache. Since we are considering the non-binding prefetch, there is a guarantee that the read operation is going to return a correct value when it is allowed to run, irrespective of the actual prefetch completion time. However, there is also a catch to this: the value read might not always be correct. Consider a case where there is a write operation performed on the memory location that was just read-prefetched. Thus the value can be read again depending on whether an invalidation-based or an update-based coherence scheme is being used. If an [http://en.wikipedia.org/wiki/Cache_coherence update-based coherence scheme] is being used, we can be assured that the other processor will send a bus update and the current processor can pick it up to update its value. However, if an invalidation based coherence scheme is used, there would be a coherence miss and the value will be read again from the system memory, giving an illusion that the prefetch did not occur.<br />
<br />
In the case of a write operation, to acquire the exclusive ownership of the line, a read-exclusive prefetch can be used. Since it is cached in the exclusive mode, a write operation can proceed without incurring an invalidate or an update on other caches which have cached the same line or block. The write operation finishes quickly because the value is already cached and there is no coherence miss, thus reducing the idle time of the processor. However, it is to be noted that the read-exclusive prefetch is only possible if the coherence scheme is invalidation-based and not update-based. The same logic of incorrectness applies here that we have seen in the read case: suppose that another processor asks for a write to the same block; in this case, the exclusive ownership will no longer be maintained. Instead the cache block will be invalidated.<br />
<br />
=== How does prefetching work ? ===<br />
<br />
In a multiprocessor environment, each processor has a [http://en.wikipedia.org/wiki/Memory_disambiguation load] and a [http://en.wikipedia.org/wiki/Memory_disambiguation store buffer]. The way in which consistency models work are that the accesses to memory locations are delayed until the previous requests have finished. While issuing a read or a write request, we can implement the prefetch by making the hardware automatically issue a prefetch for requests which are in the load or store buffer and those requests which cannot be honored right away because of the delays incurred due to consistency model constraints. <br />
<br />
Let us trace through the steps a prefetch request would follow. First, it looks up the cache to see whether the block is already present. If it is indeed available, the request is terminated. If it is not present, the prefetch is issued to memory. Depending on the type of prefetch technique we are using, the response to the prefetch may or may not be immediate. The response is then placed in the cache. This process can be optimized by detecting duplicate requests to the same location and then combining the responses to each individual request to point to the prefetch request, thereby preventing duplicate requests being issued to memory. This mechanism also taxes the system in the form of requirements. Firstly, it requires that hardware coherent caches and the block that is prefetched should fit into the cache. Then for the write prefetch to work efficiently, there should be an invalidation-based coherence scheme in place. Additionally, the bus bandwidth should be high in order to handle several prefetch requests at the same time. The caches will also be more busy with read/write transactions when prefetching is implemented.<ref>[http://www.opensparc.net/pubs/papers/InstrPfHPCA05.pdf Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications]</ref> <br />
<br />
The amount of lookahead we do for a prefetch needs to be controlled, in the sense that if a higher number of blocks are prefetched than are required, then the processor might not ever use them and it would also result in increased cache misses of actually required blocks. Thus the extent to which lookahead is done should dynamically adjust depending on whether the processor actually uses the blocks or just evicts them without a read or a write reference to it.<br />
<br />
== Prefetching with Sequential Consistency ==<br />
<br />
Sequential Consistency (SC) might cause a reader to assume that its implementation will need a single memory module. However, this is not true. Both SC and the relaxed memory models allow many optimizations within them in order to deliver high performance. SC and the relaxed models allow non-binding prefetching along with coherent caching.<ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&sqi=2&ved=0CCkQFjAA&url=ftp%3A%2F%2Fftp.cs.wisc.edu%2Fpub%2Ftechreports%2F1991%2FTR1006.pdf&ei=cZ57T-j7DNCbtwenqIG1CA&usg=AFQjCNHtHiuYi2hYaVbTkSuELNg7PNQuXA&sig2=VFMR7Hq3ofiDnH8tzbFNUg Cache consistency and sequential consistency]</ref><br />
<br />
'''Let us take a look at an example and see how SC vs prefetching with SC performs'''<br />
<br />
The assumptions being made are that the processor has non-blocking reads with branch prediction machinery, an invalidation-based cache coherence scheme is in place, if there is a cache hit the latency is 1 clock cycle, and the cache miss incurs a latency of 100 clock cycles. <br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Since we are considering a system with SC, we know that an access to memory cannot be issued until the previous access has completed. The first three accesses are misses and they occur one after the other without any interleaving, which gives us a total latency of 100 x 3 = 300 clock cycles. The fourth operation however is a cache hit, thus adding only 1 clock cycle. The four accesses take up 301 clock cycles to complete.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance. Since the system has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
Comparing the 103 clock cycles in prefetching under SC .vs. SC only we see that there is nearly a 200 clock cycle difference, which is a significant improvement. As the number of accesses increase, the difference is only going to get larger until a certain point where "SC only" would no longer be a viable option.<br />
<br />
'''Another example showing how SC vs prefetching with SC performs'''<br />
<br />
The same assumptions are being made which we made for the first example.<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under SC only we see that the total number of clock cycles are 302.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching, we see that the total time taken will be 203 (2 misses & 3 hits).<br />
<br />
Thus again, we see that prefetching with SC performs better than "SC only".<br />
<br />
== Performance of prefetching with SC and why the idea has not been widely adopted ==<br />
<br />
We have seen two examples where prefetching with SC does a better job than "SC only". However, what we need to look at is whether this is the maximum performance which we can extract. Consider the second example where we had 3 reads in a critical section. The address which E[D] is trying to access will depend on the value of D. Read D was a cache hit, and E[D] is not allowed to perform under SC until the read C finishes. Thus, even though prefetching increases performance by reducing the time delay caused due to consistency constraints, it does not deal with situations where out of order usage of the values returned by memory access is critical for the processor to proceed efficiently. In other words, prefetching fails to do a good job when out of order consumption of values is important.<ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 Memory access dependencies in shared-memory multiprocessors]</ref><ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CDIQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.52.9935%26rep%3Drep1%26type%3Dpdf&ei=wp17T_vaKsrEtwe9yvSpCA&usg=AFQjCNGQXk84yrSUHkZU-mDw0D8KMVb6WQ&sig2=rhKqMuWKvTBHdFgK3rOthw Performance evaluation of memory consistency models for shared-memory multiprocessors]</ref><br />
<br />
Even though the main use of prefetching is to enable servicing of the requests faster when compared to the delay constraints imposed by the memory contraint models, correctness needs to be maintained at all times. The number of times a prefetched value is incorrect should be small, and luckily this is indeed true in real world systems for several reasons. The invalidation of the prefetched values is loosely coupled with the delay to obtain a correct execution sequence. These delays are imposed by the memory consistency models, and in SC, which is the strictest of all models, many delays are imposed. Usually, the time when one process releases a synchronization is much earlier when compared another process trying to acquire it. Thus the delays introduced by SC are unnecessary and therefore it taxes the systems performance. <ref>[http://dl.acm.org/citation.cfm?id=285991 Memory access buffering in multiprocessors]</ref><br />
<br />
Such cases are not rare to find in real applications and hence prefetching cannot be used all the time. Therefore, prefetching under SC was not widely adopted and hence new schemes had to be developed in order to overcome the drawbacks of the current method.<br />
<br />
== Solution#1 Prefetching with Release Consistency ==<br />
<br />
Prefetching under release consistency (RC) does at least as good as prefetching under SC. Let us evaluate its performance in the two examples we looked at previously. We follow the same assumptions about the system which we have followed previously.<br />
<br />
'''The first example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Since we are considering a system with RC, we know that write accesses to memory are delayed until the lock access can be performed. The lock L operation takes 100 clock cycles to finish, followed by another 100+1 cycles for write A, write B to finish and then finally the fourth operation takes 1 clock cycle to finish because it is a hit. Thus the total number of clock cycles are 202 under the "RC only" approach.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we can get significant improvement in terms of performance, at least compared to SC. Since the system now has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
In this example, we found that prefetching with SC and prefetching with RC take the amount of time.<br />
<br />
'''The second example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under "RC only" we can see that the total number of clock cycles are 203.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we see that the total time taken will be 202 (2 misses & 2 hits pipelined).<br />
<br />
Thus again, we see that prefetching with RC performs better than "RC only".<br />
<br />
However, we have not got a significant performance gain in the second example. Thus even though RC allows more relaxation on the order of operations issued to memory, the gain is not much. Relaxed models offer more options on the hardware implementation perspective than SC, so we might get tempted to conclude that hardware must use the relaxed models instead of SC. On the other hand, the performance gain we expect to get is not being delivered under prefetching with RC, thus it cannot be justified to be a good approach either, even though it performs better than prefetching under SC.<br />
<br />
Also, the same argument that we used for SC by mentioning that it taxes the system by causing unwanted delays to ensure correctness can be applied to the RC model as well. Though unlike SC, it may not tax the system's performance much, because in RC the delays are only inserted at synchronization points. Even then it forms a part of the argument that prefetching under RC is not a very good method.<br />
<br />
== Solution#2 Speculative Execution ==<br />
<br />
Speculative execution does impose many constraints which relaxed and SC implementations do, but rather it allows them to be more aggressive. Speculative execution allows the processor to execute instructions eagerly. However, the same strictness applies when it comes to being correct. That is, the instructions must be undone when speculations prove incorrect. This scenario can be found in wrongly predicted branches. When the processor knows that it cannot be wrong, it does a commit of the instruction, which frees up the resources that were being used for implementation. There are two strict rules about instructions being committed: <ref>[http://en.wikipedia.org/wiki/Speculative_execution Speculative Execution wiki article]</ref><br />
<br />
- All instructions prior to the current instruction must be committed, &<br />
- The current instruction operation commits.<br />
<br />
For example, when we consider a load or store operation, we can be assured that it commits when it does a read or a write on a memory value. With speculative execution, both relaxed and SC implementations can perform operations out-of-order and in a speculative fashion. Consider the comparison of the peer performance of relaxed .vs. SC:<br />
<br />
read A (miss)<br />
read B (hit)<br />
<br />
When dealing with SC, read A occurs first, gets committed and then read B gets committed. However, with relaxed models, read B can get committed before read A gets committed. The difference in performance between relaxed and SC is very narrow. However, the measurement of the difference in performance depends upon benchmarks, latencies, etc.<br />
<br />
The figure below shows an example implementation of a SE system.<ref>[http://www.csl.cornell.edu/courses/ee572/gharachorloo.icpp91.pdf Two Techniques to Enhance the Performance of Memory Consistency Models by Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]</ref><br />
<br />
[[File:SE_implementation.png|600px|Example implementation of a SE system. Source: Two Techniques to Enhance the Performance of Memory Consistency Models by<br />
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]]<br />
<br />
=== Idea behind speculative execution ===<br />
<br />
The core idea which forms the crux of speculative execution is simple and easy to understand. For example, let us consider there are two accesses a and b in the program order. a is considered to have a large latency whereas b is simply a load access. Also, the consistency model needs a to complete before b can finish. The speculative execution for load accesses proceeds as follows. The processor obtains the value returned by access b before a can complete and it proceeds. Now when a completes, the processor checks to see if the speculated return value of b before the completion of a is same as the actual value obtained after a completes. If they both match then the speculation was correct and the processor proceeds without any undo of instructions. However, if the values do not match then we need to redo access b to get the correct value <ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDUQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.57.1560%26rep%3Drep1%26type%3Dpdf&ei=lbB8T8DZKtKCtgeJ7v3mDA&usg=AFQjCNElr6qsvxH41INvR6tY12S4mDwLeQ&sig2=dk_gxOC4J7VEPz3I5EOgXA Speculative Execution in Real-Time Systems]</ref>. These steps in speculative execution can be summarized by 3 different mechanisms. Namely,<br />
<br />
a) The speculative mechanism<br />
b) The detection mechanism<br />
c) The correction mechanism<br />
<br />
'''a) The speculative mechanism -''' In the speculative mechanism, the most appropriate thing to do would be to perform the access, get the returned value and proceed to use the returned value. If there is a cache hit, the value will be returned instantly, otherwise if it is a miss the access is pipelined with other accesses just like we have seen in prefetching.<br />
<br />
'''b) The detection mechanism -''' The way to detect if the speculated value is correct or not is by redoing the access after the consistency model would have actually allowed it do be done without speculation. This however might not be the only way. If we could monitor the coherence transactions on that particular location in the cache to see if there is an invalidation, then the detection process can be faster. Thus another improvement when compared to the prefetch technique is that, in speculative execution, the cache is only accessed once unlike twice, which is the norm in prefetch technique. Going back to our example of two accesses a and b, the consistency model requires that access b is deferred until access a is complete. However, under the speculative execution, b can proceed without waiting for a to complete. The detection mechanism works by monitoring whether there is an update or invalidation at location b, which is an indication that the speculation is incorrect. However, if there are no update or invalidation messages, we can be assured that the speculated value was correct.<br />
<br />
'''c) The correction mechanism -''' Once the detection mechanism determines that the speculated value is incorrect, the correction mechanism comes into play. The first step that the correction mechanism does is that it discards the computation of the speculated value. The load accesses and the computations after the speculated value can be discarded too, just like the correction mechanism used in processors when there is a branch prediction that has gone wrong.<br />
<br />
The figure below, shows the organization of a load/store functional unit of a SE system.<br />
<br />
[[File:Load_store.png|600px|Organization of a load store functional unit]]<br />
<br />
The speculative mechanism is superior to the prefetch mechanism (both under SC and RC) by giving an opportunity to use out of order speculated values.<br />
<br />
'''Referring back to the example we discussed while talking about performance of prefetching with RC/SC'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
The pipelining in both prefetching and speculative execution will be same and thus we might expect the same level of performance. But in this case, read D does not cause a bottle neck because under speculative execution; its value can be immediately consumed before the previous accesses commit. Thus we expect both the SC and RC implementations to finish in 104 clock cycles (analogous to 4 hits and 1 miss).<br />
<br />
As soon as we know the address for the access, the load access can be issued under speculative execution irrespective of the consistency model that is being supported. Even speculative execution will impose requirements on the system. For all the three mechanisms discussed, we expect hardware support, else we might not get the performance gain that we expect if we implement the same in software.<ref>[http://impact.crhc.illinois.edu/ftp/conference/micro-93-suppression.pdf Speculative Execution Exception Recovery using Write-back Suppression]</ref><br />
<br />
=== Illustrative example ===<br />
<br />
This is the example which we will be taking up for discussion to see how SE works:<br />
<br />
[[File:SE_example.png|600px|Organization of a load store functional unit]]<br />
<br />
In the above figure, the contents of various buffers are showed along with the cache content for each event that occurs. All three mechanisms which we have discussed will be traced in the example. The reorder buffer holds the instructions that are fetched and decoded. Tracing through the set of events, initially the loads and prefetches (exclusive mode) are issued for the corresponding stores. In the meantime, while the store buffer is working on the store operations, the speculative load buffer has three loads. The returned value of read D has already been used by the processor. The second event indicates an ownership for B, however it is not immediately completed. Its completion has been reordered and delayed by the reorder buffer. The third event indicates that the value of A arrives and the entries for A are purged from both the speculative-load and reorder buffers. Once the load A completes, the reorder buffer signals the store buffer to allow the store B to complete, and this is a hit because the value is already cached and thus finishes quickly. Store C is next to be served in the reorder buffer and its access is merged with the previous prefetch request for the same location.<ref>[http://www.cs.waikato.ac.nz/timewarp/wengine/papers/gc99_1/ Data and Control Speculative Execution]</ref><br />
<br />
Now to make things interesting, let us assume that there is an invalidation for D. This would cause a mismatch in the value speculated for D and hence the load D and the instructions following it are purged, indicated by event 5. The 6th event shows the correction mechanism by fetching the two instructions again and yet again load D will be a speculative event because store C has not finished. The 7th event shows new value in location D and since it is cached and its value known, E[D] proceeds. The 8th event shows that store C has finished, and since it does not affect D, the speculative value is correct and and is retired from the reorder and speculative-load buffers. The last event signifies the completion of E[D].<br />
<br />
== Future directions and ambitious implementations ==<br />
<br />
The paper by Adve and Hill <ref>[ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.pdf Implementing Sequential Consistency In Cache-Based Systems]</ref> proposes an implementation for sequential consistency that is more efficient than conventional implementations. Their scheme requires an invalidation-based cache coherence protocol. At points where a conventional implementation stalls for the full latency of pending writes, their implementation stalls only until ownership is gained. To make the implementation satisfy sequential consistency, the new value written is not made visible to other processors until all previous writes by this processor have completed. The gains from this are expected to be limited, however, since the latency of obtaining ownership is often only slightly smaller than the latency for the write to complete. In addition, the proposed scheme has no provision for hiding the latency of read accesses. Since the visibility-control mechanism reduces the stall time for writes only slightly and does not affect the stall time for reads, its performance wont be much better than conventional implementations. In contrast, the prefetch and speculative load techniques provide much greater opportunity for buffering and pipelining of read and write accesses.<br />
<br />
The paper by Stenstrom <ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 A latency-hiding scheme for multiprocessors with buffered multistage networks]</ref> proposes a mechanism for guaranteeing access order at the memory instead of at the processor. Each request contains a processor identification and a sequence number. Consecutive requests from the same processor get consecutive sequence numbers. Each memory module has access to a common data structure called next sequence-number table (NST). The NST contains P entries, one entry per processor. Each entry contains the sequence number of the next request to be performed by the corresponding processor. This allows the mechanism to guarantee that accesses from each processor are kept in program order. Theoretically, this scheme can enhance the performance of sequential consistency. However, the major disadvantage is that caches are not allowed. This can severely hinder the performance when compared to implementations that allow shared locations to be cached.<br />
<br />
To gain significant improvement in terms of performance, there have been a number of memory consistency models proposed. One disadvantage of the relaxed memory consistency models is that they present a more complex programming model to the user. The cost of this added performance benefit is however the extra hardware complexity that comes with it. The prefetch technique is simple and can easily be absorbed into the modern multi processor architectures while the speculative execution technique is not that easy when compared to the prefetch technique. Things get more complicated when the speculative execution technique is to be incorporated into multi processor systems when compared to uni processor systems. In future, we might expect better implementations of the speculative execution technique which will make this transition easy.<br />
<br />
== References ==<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/10a_vm&diff=61628CSC/ECE 506 Spring 2012/10a vm2012-04-06T15:00:44Z<p>Mbplautz: Section IV</p>
<hr />
<div>Prefetching and consistency models.<br />
== Prefetching ==<br />
<br />
=== Introduction to prefetching ===<br />
<br />
Almost all processors today use [http://en.wikipedia.org/wiki/Instruction_prefetch prefetching] as a means to speed up execution. Primarily, prefetching is used to shorten the amount of time a processor is in the wait state by predicting which cache block would be accessed next, so that when a [http://en.wikipedia.org/wiki/CPU_cache#Cache_miss cache miss] occurs, the old block in the cache can be immediately replaced with the block that is prefetched and hence decreasing the idle time of the processor. Performance in prefetching is best when it is done by following the [http://en.wikipedia.org/wiki/Out-of-order_execution program order]. However, it need not always be that prefetching is done in program order; a processor trying to guess the result of a calculation during a complex [http://en.wikipedia.org/wiki/Branch_prediction branch prediction] algorithm will need to anticipate the result and fetch the right set of instructions for execution. Things get more complex when it comes to graphical processing units or GPUs. Prefetching can take advantage of [http://en.wikipedia.org/wiki/Coherence_(physics)#Spatial_coherence spatial coherence] and the data that is prefetched are not a set of instructions, but instead they are texture elements that can be mapped to a polygon.<ref>[http://en.wikipedia.org/wiki/Instruction_prefetch Instruction prefetch wiki article.]</ref><br />
<br />
=== Types of prefetching ===<br />
<br />
[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] can be primarily classified based on whether it is binding or non-binding, and whether it is hardware or software controlled. Using a binding prefetch, the value of a later reference, like a register load, is bound at the time the prefetch completes. However, this comes with added restrictions because the value in the prefetch might not be accurate - there might be invalidations that can be caused by another processor in the time frame between prefetch and reference by the current processor. Coming to the non-binding prefetch case, the data is stored into the processor cache, and the coherence is maintained till the processor reads or writes the value. This approach, unlike binding prefetch, will not have an effect on the correctness of any consistency model. It can serve as a serious improvement in terms of performance.<br />
<br />
The prefetch that is interesting to us is the hardware controlled and non-binding prefetch. Prefetching done in software involves significant effort from the programmer's side, and it may not be scalable as the length of the program increases. In comparison, the non-binding prefetch yields significantly more performance when compared to the binding prefetch. The major performance enhancement from prefetching comes by decreasing the memory latencies that are caused by all consistency models. <br />
<br />
In the case of a read operation, the read prefetch is issued to get the data in a read-only shared state in the cache. Since we are considering the non-binding prefetch, there is a guarantee that the read operation is going to return a correct value when it is allowed to run, irrespective of the actual prefetch completion time. However, there is also a catch to this: the value read might not always be correct. Consider a case where there is a write operation performed on the memory location that was just read-prefetched. Thus the value can be read again depending on whether an invalidation-based or an update-based coherence scheme is being used. If an [http://en.wikipedia.org/wiki/Cache_coherence update-based coherence scheme] is being used, we can be assured that the other processor will send a bus update and the current processor can pick it up to update its value. However, if an invalidation based coherence scheme is used, there would be a coherence miss and the value will be read again from the system memory, giving an illusion that the prefetch did not occur.<br />
<br />
In the case of a write operation, to acquire the exclusive ownership of the line, a read-exclusive prefetch can be used. Since it is cached in the exclusive mode, a write operation can proceed without incurring an invalidate or an update on other caches which have cached the same line or block. The write operation finishes quickly because the value is already cached and there is no coherence miss, thus reducing the idle time of the processor. However, it is to be noted that the read-exclusive prefetch is only possible if the coherence scheme is invalidation-based and not update-based. The same logic of incorrectness applies here that we have seen in the read case: suppose that another processor asks for a write to the same block; in this case, the exclusive ownership will no longer be maintained. Instead the cache block will be invalidated.<br />
<br />
=== How does prefetching work ? ===<br />
<br />
In a multiprocessor environment, each processor has a [http://en.wikipedia.org/wiki/Memory_disambiguation load] and a [http://en.wikipedia.org/wiki/Memory_disambiguation store buffer]. The way in which consistency models work are that the accesses to memory locations are delayed until the previous requests have finished. While issuing a read or a write request, we can implement the prefetch by making the hardware automatically issue a prefetch for requests which are in the load or store buffer and those requests which cannot be honored right away because of the delays incurred due to consistency model constraints. <br />
<br />
Let us trace through the steps a prefetch request would follow. First, it looks up the cache to see whether the block is already present. If it is indeed available, the request is terminated. If it is not present, the prefetch is issued to memory. Depending on the type of prefetch technique we are using, the response to the prefetch may or may not be immediate. The response is then placed in the cache. This process can be optimized by detecting duplicate requests to the same location and then combining the responses to each individual request to point to the prefetch request, thereby preventing duplicate requests being issued to memory. This mechanism also taxes the system in the form of requirements. Firstly, it requires that hardware coherent caches and the block that is prefetched should fit into the cache. Then for the write prefetch to work efficiently, there should be an invalidation-based coherence scheme in place. Additionally, the bus bandwidth should be high in order to handle several prefetch requests at the same time. The caches will also be more busy with read/write transactions when prefetching is implemented.<ref>[http://www.opensparc.net/pubs/papers/InstrPfHPCA05.pdf Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications]</ref> <br />
<br />
The amount of lookahead we do for a prefetch needs to be controlled, in the sense that if a higher number of blocks are prefetched than are required, then the processor might not ever use them and it would also result in increased cache misses of actually required blocks. Thus the extent to which lookahead is done should dynamically adjust depending on whether the processor actually uses the blocks or just evicts them without a read or a write reference to it.<br />
<br />
== Prefetching with Sequential Consistency ==<br />
<br />
Sequential Consistency (SC) might cause a reader to assume that its implementation will need a single memory module. However, this is not true. Both SC and the relaxed memory models allow many optimizations within them in order to deliver high performance. SC and the relaxed models allow non-binding prefetching along with coherent caching.<ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&sqi=2&ved=0CCkQFjAA&url=ftp%3A%2F%2Fftp.cs.wisc.edu%2Fpub%2Ftechreports%2F1991%2FTR1006.pdf&ei=cZ57T-j7DNCbtwenqIG1CA&usg=AFQjCNHtHiuYi2hYaVbTkSuELNg7PNQuXA&sig2=VFMR7Hq3ofiDnH8tzbFNUg Cache consistency and sequential consistency]</ref><br />
<br />
'''Let us take a look at an example and see how SC vs prefetching with SC performs'''<br />
<br />
The assumptions being made are that the processor has non-blocking reads with branch prediction machinery, an invalidation-based cache coherence scheme is in place, if there is a cache hit the latency is 1 clock cycle, and the cache miss incurs a latency of 100 clock cycles. <br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Since we are considering a system with SC, we know that an access to memory cannot be issued until the previous access has completed. The first three accesses are misses and they occur one after the other without any interleaving, which gives us a total latency of 100 x 3 = 300 clock cycles. The fourth operation however is a cache hit, thus adding only 1 clock cycle. The four accesses take up 301 clock cycles to complete.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance. Since the system has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
Comparing the 103 clock cycles in prefetching under SC .vs. SC only we see that there is nearly a 200 clock cycle difference, which is a significant improvement. As the number of accesses increase, the difference is only going to get larger until a certain point where "SC only" would no longer be a viable option.<br />
<br />
'''Another example showing how SC vs prefetching with SC performs'''<br />
<br />
The same assumptions are being made which we made for the first example.<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under SC only we see that the total number of clock cycles are 302.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching, we see that the total time taken will be 203 (2 misses & 3 hits).<br />
<br />
Thus again, we see that prefetching with SC performs better than "SC only".<br />
<br />
== Performance of prefetching with SC and why the idea has not been widely adopted ==<br />
<br />
We have seen two examples where prefetching with SC does a better job than "SC only". However, what we need to look at is whether this is the maximum performance which we can extract. Consider the second example where we had 3 reads in a critical section. The address which E[D] is trying to access will depend on the value of D. Read D was a cache hit, and E[D] is not allowed to perform under SC until the read C finishes. Thus, even though prefetching increases performance by reducing the time delay caused due to consistency constraints, it does not deal with situations where out of order usage of the values returned by memory access is critical for the processor to proceed efficiently. In other words, prefetching fails to do a good job when out of order consumption of values is important.<ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 Memory access dependencies in shared-memory multiprocessors]</ref><ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CDIQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.52.9935%26rep%3Drep1%26type%3Dpdf&ei=wp17T_vaKsrEtwe9yvSpCA&usg=AFQjCNGQXk84yrSUHkZU-mDw0D8KMVb6WQ&sig2=rhKqMuWKvTBHdFgK3rOthw Performance evaluation of memory consistency models for shared-memory multiprocessors]</ref><br />
<br />
Even though the main use of prefetching is to enable servicing of the requests faster when compared to the delay constraints imposed by the memory contraint models, correctness needs to be maintained at all times. The number of times a prefetched value is incorrect should be small, and luckily this is indeed true in real world systems for several reasons. The invalidation of the prefetched values is loosely coupled with the delay to obtain a correct execution sequence. These delays are imposed by the memory consistency models, and in SC, which is the strictest of all models, many delays are imposed. Usually, the time when one process releases a synchronization is much earlier when compared another process trying to acquire it. Thus the delays introduced by SC are unnecessary and therefore it taxes the systems performance. <ref>[http://dl.acm.org/citation.cfm?id=285991 Memory access buffering in multiprocessors]</ref><br />
<br />
Such cases are not rare to find in real applications and hence prefetching cannot be used all the time. Therefore, prefetching under SC was not widely adopted and hence new schemes had to be developed in order to overcome the drawbacks of the current method.<br />
<br />
== Solution#1 Prefetching with Release Consistency ==<br />
<br />
Prefetching under release consistency (RC) does at least as good as prefetching under SC. Let us evaluate its performance in the two examples we looked at previously. We follow the same assumptions about the system which we have followed previously.<br />
<br />
'''The first example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Since we are considering a system with RC, we know that write accesses to memory are delayed until the lock access can be performed. The lock L operation takes 100 clock cycles to finish, followed by another 100+1 cycles for write A, write B to finish and then finally the fourth operation takes 1 clock cycle to finish because it is a hit. Thus the total number of clock cycles are 202 under the "RC only" approach.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we can get significant improvement in terms of performance, at least compared to SC. Since the system now has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
In this example, we found that prefetching with SC and prefetching with RC take the amount of time.<br />
<br />
'''The second example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under "RC only" we can see that the total number of clock cycles are 203.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we see that the total time taken will be 202 (2 misses & 2 hits pipelined).<br />
<br />
Thus again, we see that prefetching with RC performs better than "RC only".<br />
<br />
However, we have not got a significant performance gain in the second example. Thus even though RC allows more relaxation on the order of operations issued to memory, the gain is not much. Relaxed models offer more options on the hardware implementation perspective than SC, so we might get tempted to conclude that hardware must use the relaxed models instead of SC. On the other hand, the performance gain we expect to get is not being delivered under prefetching with RC, thus it cannot be justified to be a good approach either, even though it performs better than prefetching under SC.<br />
<br />
Also, the same argument that we used for SC by mentioning that it taxes the system by causing unwanted delays to ensure correctness can be applied to the RC model as well. Though unlike SC, it may not tax the system's performance much, because in RC the delays are only inserted at synchronization points. Even then it forms a part of the argument that prefetching under RC is not a very good method.<br />
<br />
== Solution#2 Speculative Execution ==<br />
<br />
Speculative execution does impose many constraints which relaxed and SC implementations do, but rather it allows them to be more aggressive. Speculative execution allows the processor to execute instructions eagerly. However the same strictness when it comes to being correct applies. That is the instructions must be undone when speculations prove incorrect. This scenario can be found in wrongly predicted branches. When the processor knows that it cannot be wrong, it does a commit of the instruction which frees up the resources that were being used for implementation. There are two strict rules about instructions being committed: <ref>[http://en.wikipedia.org/wiki/Speculative_execution Speculative Execution wiki article]</ref><br />
<br />
- All instructions prior to the current instruction must be committed, &<br />
- The current instruction operation commits.<br />
<br />
For example, when we consider a load or store operation, we can be assured that it commits when it does a read or a write on a memory value. With speculative execution, both relaxed and SC implementations can perform operations out of order and in a speculative fashion. While comparing the peer performance of relaxed .vs. SC,<br />
<br />
read A (miss)<br />
read B (hit)<br />
<br />
When dealing with SC, read A occurs first, gets committed and then read B gets committed. However, with relaxed models, read B can get committed before read A gets committed. The difference in performance between relaxed and SC is very narrow. However, the measurement of the difference in performance depends upon benchmarks, latencies etc.<br />
<br />
The figure below shows an example implementation of a SE system.<ref>[http://www.csl.cornell.edu/courses/ee572/gharachorloo.icpp91.pdf Two Techniques to Enhance the Performance of Memory Consistency Models by Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]</ref><br />
<br />
[[File:SE_implementation.png|600px|Example implementation of a SE system. Source: Two Techniques to Enhance the Performance of Memory Consistency Models by<br />
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]]<br />
<br />
=== Idea behind speculative execution ===<br />
<br />
The core idea which forms the crux of speculative execution is simple and easy to understand. For example, let us consider there are two accesses a and b in the program order. a is considered to have a large latency whereas b is simply a load access. Also, the consistency model needs a to complete before b can finish. The speculative execution for load accesses proceeds as follows. The processor obtains the value returned by access b before a can complete and it proceeds. Now when a completes, the processor checks to see if the speculated return value of b before the completion of a is same as the actual value obtained after a completes. If they both match then the speculation was correct and the processor proceeds without any undo of instructions. However, if the values do not match then we need to redo access b to get the correct value <ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDUQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.57.1560%26rep%3Drep1%26type%3Dpdf&ei=lbB8T8DZKtKCtgeJ7v3mDA&usg=AFQjCNElr6qsvxH41INvR6tY12S4mDwLeQ&sig2=dk_gxOC4J7VEPz3I5EOgXA Speculative Execution in Real-Time Systems]</ref>. These steps in speculative execution can be summarized by 3 different mechanisms. Namely,<br />
<br />
a) The speculative mechanism<br />
b) The detection mechanism<br />
c) The correction mechanism<br />
<br />
'''a) The speculative mechanism -''' In the speculative mechanism, the most appropriate thing to do would be to perform the access, get the returned value and proceed to use the returned value. If there is a cache hit, the value will be returned instantly, else if it is a miss the access is pipelined with other accesses just like we have seen in prefetching.<br />
<br />
'''b) The detection mechanism -''' The way to detect if the speculated value is correct or not, is by redoing the access after the consistency model would have actually allowed it do be done without speculation. This however might not be the only way. If we could monitor the coherence transactions on that particular location in cache to see if there is an invalidation then the detection process can be faster. Thus another improvement when compared to the prefetch technique is that, in speculative execution the cache is only accessed once unlike twice which is the norm in prefetch technique. Going back to our example of two accesses a and b, the consistency model requires that access b is deferred until access a is complete. However, under the speculative execution, b can proceed without waiting for a to complete. The detection mechanism works by monitoring whether there is an update or invalidation at location b which is an indication that the speculation is incorrect. However, if there are no update or invalidation messages, we can be assured that the speculated value was correct.<br />
<br />
'''c) The correction mechanism -''' Once the detection mechanism determines that the speculated value is incorrect, the correction mechanism comes into play. The first step that the correction mechanism does is that it discards the computation of the speculated value. The load accesses and the computations after the speculated value can be discarded too, just like the correction mechanism used in processors when there is a branch prediction that has gone wrong.<br />
<br />
The figure below, shows the organization of a load/store functional unit of a SE system.<br />
<br />
[[File:Load_store.png|600px|Organization of a load store functional unit]]<br />
<br />
The speculative mechanism is superior to the prefetch mechanism (both under SC and RC) by giving an opportunity to use out of order speculated values.<br />
<br />
'''Referring back to the example we discussed while talking about performance of prefetching with RC/SC'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
The pipelining in both prefetching and speculative execution will be same and thus we might expect the same level of performance. But however read D does not cause a bottle neck because under speculative execution, its value can be immediately consumed before the previous accesses commit. Thus we expect both the SC and RC implementations to finish in 104 clock cycles (analogous to 4 hits and 1 miss).<br />
<br />
As soon as we know the address for the access, the load access can be issued under speculative execution irrespective of the consistency model that is being supported. Even speculative execution will impose requirements on the system. For all the three mechanisms discussed, we expect hardware support, else we might not get the performance gain that we expect if we implement the same in software.<ref>[http://impact.crhc.illinois.edu/ftp/conference/micro-93-suppression.pdf Speculative Execution Exception Recovery using Write-back Suppression]</ref><br />
<br />
=== Illustrative example ===<br />
<br />
This is the example which we will be taking up for discussion to see how SE works,<br />
<br />
[[File:SE_example.png|600px|Organization of a load store functional unit]]<br />
<br />
In the above figure, the contents of various buffers are showed along with the cache content for each event that occurs. All three mechanisms which we have discussed will be traced in the example. The reorder buffer holds the instructions that are fetched and decoded. Tracing through the set of events, initially the loads and prefetches (exclusive mode) are issued for the corresponding stores. In the meantime, while the store buffer is working on the store operations, the speculative load buffer has three loads. The returned value of read D has already been used by the processor. The second event indicates an ownership for B, however it is not immediately completed. Its completion has been reordered and delayed by the reorder buffer. The third event indicates that the value of A arrives and the entrees for A are purged from both the speculative-load and reorder buffers. Once the load A completes the reorder buffer signals the store buffer to allow the store B to complete. And this is a hit because the value is already cached and thus finishes quickly. Store C is next to be served in the reorder buffer and its access is merged with the previous prefetch request for the same location.<ref>[http://www.cs.waikato.ac.nz/timewarp/wengine/papers/gc99_1/ Data and Control Speculative Execution]</ref><br />
<br />
Now to make things interesting, let us assume that there is an invalidation for D. This would cause a mismatch in the value speculated for D and hence the load D and the instructions following it are purged, indicated by event 5. The 6th event shows the correction mechanism by fetching the two instructions again and yet again load D will be a speculative event because store C has not finished. The 7th event shows new value in location D and since it is cached and its value known, E[D] proceeds. The 8th event shows that store C has finished and since it does not effect D, the speculative value is correct and and is retired from the reorder and speculative-load buffers. The last even signifies the completion of E[D].<br />
<br />
== Future directions and ambitious implementations ==<br />
<br />
The paper by Adve and Hill <ref>[ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.pdf Implementing Sequential Consistency In Cache-Based Systems]</ref> proposes an implementation for sequential consistency that is more efficient than conventional implementations. Their scheme requires an invalidation-based cache coherence protocol. At points where a conventional implementation stalls for the full latency of pending writes, their implementation stalls only until ownership is gained. To make the implementation satisfy sequential consistency, the new value written is not made visible to other processors until all previous writes by this processor have completed. The gains from this are expected to be limited, however, since the latency of obtaining ownership is often only slightly smaller than the latency for the write to complete. In addition, the proposed scheme has no provision for hiding the latency of read accesses. Since the visibility-control mechanism reduces the stall time for writes only slightly and does not affect the stall time for reads, its performance wont be much better than conventional implementations. In contrast, the prefetch and speculative load techniques provide much greater opportunity for buffering and pipelining of read and write accesses.<br />
<br />
The paper by Stenstrom <ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 A latency-hiding scheme for multiprocessors with buffered multistage networks]</ref> proposes a mechanism for guaranteeing access order at the memory instead of at the processor. Each request contains a processor identification and a sequence number. Consecutive requests from the same processor get consecutive sequence numbers. Each memory module has access to a common data structure called next sequence-number table (NST). The NST contains P entries, one entry per processor. Each entry contains the sequence number of the next request to be performed by the corresponding processor. This allows the mechanism to guarantee that accesses from each processor are kept in program order. Theoretically, this scheme can enhance the performance of sequential consistency. However, the major disadvantage is that caches are not allowed. This can severely hinder the performance when compared to implementations that allow shared locations to be cached.<br />
<br />
To gain significant improvement in terms of performance, there have been a number of memory consistency models proposed. One disadvantage of the relaxed memory consistency models is that they present a more complex programming model to the user. The cost of this added performance benefit is however the extra hardware complexity that comes with it. The prefetch technique is simple and can easily be absorbed into the modern multi processor architectures while the speculative execution technique is not that easy when compared to the prefetch technique. Things get more complicated when the speculative execution technique is to be incorporated into multi processor systems when compared to uni processor systems. In future, we might expect better implementations of the speculative execution technique which will make this transition easy.<br />
<br />
== References ==<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/10a_vm&diff=61627CSC/ECE 506 Spring 2012/10a vm2012-04-06T14:48:14Z<p>Mbplautz: Section III</p>
<hr />
<div>Prefetching and consistency models.<br />
== Prefetching ==<br />
<br />
=== Introduction to prefetching ===<br />
<br />
Almost all processors today use [http://en.wikipedia.org/wiki/Instruction_prefetch prefetching] as a means to speed up execution. Primarily, prefetching is used to shorten the amount of time a processor is in the wait state by predicting which cache block would be accessed next, so that when a [http://en.wikipedia.org/wiki/CPU_cache#Cache_miss cache miss] occurs, the old block in the cache can be immediately replaced with the block that is prefetched and hence decreasing the idle time of the processor. Performance in prefetching is best when it is done by following the [http://en.wikipedia.org/wiki/Out-of-order_execution program order]. However, it need not always be that prefetching is done in program order; a processor trying to guess the result of a calculation during a complex [http://en.wikipedia.org/wiki/Branch_prediction branch prediction] algorithm will need to anticipate the result and fetch the right set of instructions for execution. Things get more complex when it comes to graphical processing units or GPUs. Prefetching can take advantage of [http://en.wikipedia.org/wiki/Coherence_(physics)#Spatial_coherence spatial coherence] and the data that is prefetched are not a set of instructions, but instead they are texture elements that can be mapped to a polygon.<ref>[http://en.wikipedia.org/wiki/Instruction_prefetch Instruction prefetch wiki article.]</ref><br />
<br />
=== Types of prefetching ===<br />
<br />
[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] can be primarily classified based on whether it is binding or non-binding, and whether it is hardware or software controlled. Using a binding prefetch, the value of a later reference, like a register load, is bound at the time the prefetch completes. However, this comes with added restrictions because the value in the prefetch might not be accurate - there might be invalidations that can be caused by another processor in the time frame between prefetch and reference by the current processor. Coming to the non-binding prefetch case, the data is stored into the processor cache, and the coherence is maintained till the processor reads or writes the value. This approach, unlike binding prefetch, will not have an effect on the correctness of any consistency model. It can serve as a serious improvement in terms of performance.<br />
<br />
The prefetch that is interesting to us is the hardware controlled and non-binding prefetch. Prefetching done in software involves significant effort from the programmer's side, and it may not be scalable as the length of the program increases. In comparison, the non-binding prefetch yields significantly more performance when compared to the binding prefetch. The major performance enhancement from prefetching comes by decreasing the memory latencies that are caused by all consistency models. <br />
<br />
In the case of a read operation, the read prefetch is issued to get the data in a read-only shared state in the cache. Since we are considering the non-binding prefetch, there is a guarantee that the read operation is going to return a correct value when it is allowed to run, irrespective of the actual prefetch completion time. However, there is also a catch to this: the value read might not always be correct. Consider a case where there is a write operation performed on the memory location that was just read-prefetched. Thus the value can be read again depending on whether an invalidation-based or an update-based coherence scheme is being used. If an [http://en.wikipedia.org/wiki/Cache_coherence update-based coherence scheme] is being used, we can be assured that the other processor will send a bus update and the current processor can pick it up to update its value. However, if an invalidation based coherence scheme is used, there would be a coherence miss and the value will be read again from the system memory, giving an illusion that the prefetch did not occur.<br />
<br />
In the case of a write operation, to acquire the exclusive ownership of the line, a read-exclusive prefetch can be used. Since it is cached in the exclusive mode, a write operation can proceed without incurring an invalidate or an update on other caches which have cached the same line or block. The write operation finishes quickly because the value is already cached and there is no coherence miss, thus reducing the idle time of the processor. However, it is to be noted that the read-exclusive prefetch is only possible if the coherence scheme is invalidation-based and not update-based. The same logic of incorrectness applies here that we have seen in the read case: suppose that another processor asks for a write to the same block; in this case, the exclusive ownership will no longer be maintained. Instead the cache block will be invalidated.<br />
<br />
=== How does prefetching work ? ===<br />
<br />
In a multiprocessor environment, each processor has a [http://en.wikipedia.org/wiki/Memory_disambiguation load] and a [http://en.wikipedia.org/wiki/Memory_disambiguation store buffer]. The way in which consistency models work are that the accesses to memory locations are delayed until the previous requests have finished. While issuing a read or a write request, we can implement the prefetch by making the hardware automatically issue a prefetch for requests which are in the load or store buffer and those requests which cannot be honored right away because of the delays incurred due to consistency model constraints. <br />
<br />
Let us trace through the steps a prefetch request would follow. First, it looks up the cache to see whether the block is already present. If it is indeed available, the request is terminated. If it is not present, the prefetch is issued to memory. Depending on the type of prefetch technique we are using, the response to the prefetch may or may not be immediate. The response is then placed in the cache. This process can be optimized by detecting duplicate requests to the same location and then combining the responses to each individual request to point to the prefetch request, thereby preventing duplicate requests being issued to memory. This mechanism also taxes the system in the form of requirements. Firstly, it requires that hardware coherent caches and the block that is prefetched should fit into the cache. Then for the write prefetch to work efficiently, there should be an invalidation-based coherence scheme in place. Additionally, the bus bandwidth should be high in order to handle several prefetch requests at the same time. The caches will also be more busy with read/write transactions when prefetching is implemented.<ref>[http://www.opensparc.net/pubs/papers/InstrPfHPCA05.pdf Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications]</ref> <br />
<br />
The amount of lookahead we do for a prefetch needs to be controlled, in the sense that if a higher number of blocks are prefetched than are required, then the processor might not ever use them and it would also result in increased cache misses of actually required blocks. Thus the extent to which lookahead is done should dynamically adjust depending on whether the processor actually uses the blocks or just evicts them without a read or a write reference to it.<br />
<br />
== Prefetching with Sequential Consistency ==<br />
<br />
Sequential Consistency (SC) might cause a reader to assume that its implementation will need a single memory module. However, this is not true. Both SC and the relaxed memory models allow many optimizations within them in order to deliver high performance. SC and the relaxed models allow non-binding prefetching along with coherent caching.<ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&sqi=2&ved=0CCkQFjAA&url=ftp%3A%2F%2Fftp.cs.wisc.edu%2Fpub%2Ftechreports%2F1991%2FTR1006.pdf&ei=cZ57T-j7DNCbtwenqIG1CA&usg=AFQjCNHtHiuYi2hYaVbTkSuELNg7PNQuXA&sig2=VFMR7Hq3ofiDnH8tzbFNUg Cache consistency and sequential consistency]</ref><br />
<br />
'''Let us take a look at an example and see how SC vs prefetching with SC performs'''<br />
<br />
The assumptions being made are that the processor has non-blocking reads with branch prediction machinery, an invalidation-based cache coherence scheme is in place, if there is a cache hit the latency is 1 clock cycle, and the cache miss incurs a latency of 100 clock cycles. <br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Since we are considering a system with SC, we know that an access to memory cannot be issued until the previous access has completed. The first three accesses are misses and they occur one after the other without any interleaving, which gives us a total latency of 100 x 3 = 300 clock cycles. The fourth operation however is a cache hit, thus adding only 1 clock cycle. The four accesses take up 301 clock cycles to complete.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance. Since the system has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
Comparing the 103 clock cycles in prefetching under SC .vs. SC only we see that there is nearly a 200 clock cycle difference, which is a significant improvement. As the number of accesses increase, the difference is only going to get larger until a certain point where "SC only" would no longer be a viable option.<br />
<br />
'''Another example showing how SC vs prefetching with SC performs'''<br />
<br />
The same assumptions are being made which we made for the first example.<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under SC only we see that the total number of clock cycles are 302.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching, we see that the total time taken will be 203 (2 misses & 3 hits).<br />
<br />
Thus again, we see that prefetching with SC performs better than "SC only".<br />
<br />
== Performance of prefetching with SC and why the idea has not been widely adopted ==<br />
<br />
We have seen two examples where prefetching with SC does a better job than "SC only". However, what we need to look at is whether this is the maximum performance which we can extract. Consider the second example where we had 3 reads in a critical section. The address which E[D] is trying to access will depend on the value of D. Read D was a cache hit, and E[D] is not allowed to perform under SC until the read C finishes. Thus, even though prefetching increases performance by reducing the time delay caused due to consistency constraints, it does not deal with situations where out of order usage of the values returned by memory access is critical for the processor to proceed efficiently. In other words, prefetching fails to do a good job when out of order consumption of values is important.<ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 Memory access dependencies in shared-memory multiprocessors]</ref><ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CDIQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.52.9935%26rep%3Drep1%26type%3Dpdf&ei=wp17T_vaKsrEtwe9yvSpCA&usg=AFQjCNGQXk84yrSUHkZU-mDw0D8KMVb6WQ&sig2=rhKqMuWKvTBHdFgK3rOthw Performance evaluation of memory consistency models for shared-memory multiprocessors]</ref><br />
<br />
Even though the main use of prefetching is to enable servicing of the requests faster when compared to the delay constraints imposed by the memory contraint models, correctness needs to be maintained at all times. The number of times a prefetched value is incorrect should be small, and luckily this is indeed true in real world systems for several reasons. The invalidation of the prefetched values is loosely coupled with the delay to obtain a correct execution sequence. These delays are imposed by the memory consistency models, and in SC, which is the strictest of all models, many delays are imposed. Usually, the time when one process releases a synchronization is much earlier when compared another process trying to acquire it. Thus the delays introduced by SC are unnecessary and therefore it taxes the systems performance. <ref>[http://dl.acm.org/citation.cfm?id=285991 Memory access buffering in multiprocessors]</ref><br />
<br />
Such cases are not rare to find in real applications and hence prefetching cannot be used all the time. Therefore, prefetching under SC was not widely adopted and hence new schemes had to be developed in order to overcome the drawbacks of the current method.<br />
<br />
== Solution#1 Prefetching with Release Consistency ==<br />
<br />
Prefetching under release consistency does at least as good as prefetching under SC. Let us evaluate its performance in the two examples we looked at previously. We follow the same assumptions about the system which we have followed previously.<br />
<br />
'''The first example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Since we are considering a system with RC, we know that write accesses to memory are delayed until the lock access can be performed. The lock L operation takes 100 clock cycles to finish, followed by another 100+1 cycles for write A, write B to finish and then finally the fourth operation takes 1 clock cycle to finish because it is a hit. Thus the total number of clock cycles are 202 under the "RC only" approach.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance, atleast with SC. Since the system now has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
In this example, we found that prefetching with SC and prefetching with RC take the amount of time.<br />
<br />
'''The second example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under "RC only" we can see that the total number of clock cycles are 203.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we see that the total time taken will be 202 (2 misses & 2 hits pipelined).<br />
<br />
Thus again, we see that prefetching with RC performs better than "RC only".<br />
<br />
However, we have not got a significant performance gain in the second example. Thus even though RC allows more relaxation on the order of operations issued to memory, the gain is not much. Relaxed models offer more options on the hardware implementation perspective than SC, so we might get tempted to conclude that hardware must use the relaxed models instead of SC. On the other hand, the performance gain we expect too get is not being delivered under prefetching with RC, thus it cannot be justified to be a good approach either. Even though it performs better than prefetching under SC.<br />
<br />
Also, the same argument that we used for SC by mentioning that it taxes the system by causing unwanted delays to ensure correctness can be applied to the RC model as well. Though unlike SC, it may not tax the systems performance much, because in RC the delays are only inserted at synchronization points. Even then it forms a part of the argument that prefetching under RC is not a very good method.<br />
<br />
== Solution#2 Speculative Execution ==<br />
<br />
Speculative execution does impose many constraints which relaxed and SC implementations do, but rather it allows them to be more aggressive. Speculative execution allows the processor to execute instructions eagerly. However the same strictness when it comes to being correct applies. That is the instructions must be undone when speculations prove incorrect. This scenario can be found in wrongly predicted branches. When the processor knows that it cannot be wrong, it does a commit of the instruction which frees up the resources that were being used for implementation. There are two strict rules about instructions being committed: <ref>[http://en.wikipedia.org/wiki/Speculative_execution Speculative Execution wiki article]</ref><br />
<br />
- All instructions prior to the current instruction must be committed, &<br />
- The current instruction operation commits.<br />
<br />
For example, when we consider a load or store operation, we can be assured that it commits when it does a read or a write on a memory value. With speculative execution, both relaxed and SC implementations can perform operations out of order and in a speculative fashion. While comparing the peer performance of relaxed .vs. SC,<br />
<br />
read A (miss)<br />
read B (hit)<br />
<br />
When dealing with SC, read A occurs first, gets committed and then read B gets committed. However, with relaxed models, read B can get committed before read A gets committed. The difference in performance between relaxed and SC is very narrow. However, the measurement of the difference in performance depends upon benchmarks, latencies etc.<br />
<br />
The figure below shows an example implementation of a SE system.<ref>[http://www.csl.cornell.edu/courses/ee572/gharachorloo.icpp91.pdf Two Techniques to Enhance the Performance of Memory Consistency Models by Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]</ref><br />
<br />
[[File:SE_implementation.png|600px|Example implementation of a SE system. Source: Two Techniques to Enhance the Performance of Memory Consistency Models by<br />
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]]<br />
<br />
=== Idea behind speculative execution ===<br />
<br />
The core idea which forms the crux of speculative execution is simple and easy to understand. For example, let us consider there are two accesses a and b in the program order. a is considered to have a large latency whereas b is simply a load access. Also, the consistency model needs a to complete before b can finish. The speculative execution for load accesses proceeds as follows. The processor obtains the value returned by access b before a can complete and it proceeds. Now when a completes, the processor checks to see if the speculated return value of b before the completion of a is same as the actual value obtained after a completes. If they both match then the speculation was correct and the processor proceeds without any undo of instructions. However, if the values do not match then we need to redo access b to get the correct value <ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDUQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.57.1560%26rep%3Drep1%26type%3Dpdf&ei=lbB8T8DZKtKCtgeJ7v3mDA&usg=AFQjCNElr6qsvxH41INvR6tY12S4mDwLeQ&sig2=dk_gxOC4J7VEPz3I5EOgXA Speculative Execution in Real-Time Systems]</ref>. These steps in speculative execution can be summarized by 3 different mechanisms. Namely,<br />
<br />
a) The speculative mechanism<br />
b) The detection mechanism<br />
c) The correction mechanism<br />
<br />
'''a) The speculative mechanism -''' In the speculative mechanism, the most appropriate thing to do would be to perform the access, get the returned value and proceed to use the returned value. If there is a cache hit, the value will be returned instantly, else if it is a miss the access is pipelined with other accesses just like we have seen in prefetching.<br />
<br />
'''b) The detection mechanism -''' The way to detect if the speculated value is correct or not, is by redoing the access after the consistency model would have actually allowed it do be done without speculation. This however might not be the only way. If we could monitor the coherence transactions on that particular location in cache to see if there is an invalidation then the detection process can be faster. Thus another improvement when compared to the prefetch technique is that, in speculative execution the cache is only accessed once unlike twice which is the norm in prefetch technique. Going back to our example of two accesses a and b, the consistency model requires that access b is deferred until access a is complete. However, under the speculative execution, b can proceed without waiting for a to complete. The detection mechanism works by monitoring whether there is an update or invalidation at location b which is an indication that the speculation is incorrect. However, if there are no update or invalidation messages, we can be assured that the speculated value was correct.<br />
<br />
'''c) The correction mechanism -''' Once the detection mechanism determines that the speculated value is incorrect, the correction mechanism comes into play. The first step that the correction mechanism does is that it discards the computation of the speculated value. The load accesses and the computations after the speculated value can be discarded too, just like the correction mechanism used in processors when there is a branch prediction that has gone wrong.<br />
<br />
The figure below, shows the organization of a load/store functional unit of a SE system.<br />
<br />
[[File:Load_store.png|600px|Organization of a load store functional unit]]<br />
<br />
The speculative mechanism is superior to the prefetch mechanism (both under SC and RC) by giving an opportunity to use out of order speculated values.<br />
<br />
'''Referring back to the example we discussed while talking about performance of prefetching with RC/SC'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
The pipelining in both prefetching and speculative execution will be same and thus we might expect the same level of performance. But however read D does not cause a bottle neck because under speculative execution, its value can be immediately consumed before the previous accesses commit. Thus we expect both the SC and RC implementations to finish in 104 clock cycles (analogous to 4 hits and 1 miss).<br />
<br />
As soon as we know the address for the access, the load access can be issued under speculative execution irrespective of the consistency model that is being supported. Even speculative execution will impose requirements on the system. For all the three mechanisms discussed, we expect hardware support, else we might not get the performance gain that we expect if we implement the same in software.<ref>[http://impact.crhc.illinois.edu/ftp/conference/micro-93-suppression.pdf Speculative Execution Exception Recovery using Write-back Suppression]</ref><br />
<br />
=== Illustrative example ===<br />
<br />
This is the example which we will be taking up for discussion to see how SE works,<br />
<br />
[[File:SE_example.png|600px|Organization of a load store functional unit]]<br />
<br />
In the above figure, the contents of various buffers are showed along with the cache content for each event that occurs. All three mechanisms which we have discussed will be traced in the example. The reorder buffer holds the instructions that are fetched and decoded. Tracing through the set of events, initially the loads and prefetches (exclusive mode) are issued for the corresponding stores. In the meantime, while the store buffer is working on the store operations, the speculative load buffer has three loads. The returned value of read D has already been used by the processor. The second event indicates an ownership for B, however it is not immediately completed. Its completion has been reordered and delayed by the reorder buffer. The third event indicates that the value of A arrives and the entrees for A are purged from both the speculative-load and reorder buffers. Once the load A completes the reorder buffer signals the store buffer to allow the store B to complete. And this is a hit because the value is already cached and thus finishes quickly. Store C is next to be served in the reorder buffer and its access is merged with the previous prefetch request for the same location.<ref>[http://www.cs.waikato.ac.nz/timewarp/wengine/papers/gc99_1/ Data and Control Speculative Execution]</ref><br />
<br />
Now to make things interesting, let us assume that there is an invalidation for D. This would cause a mismatch in the value speculated for D and hence the load D and the instructions following it are purged, indicated by event 5. The 6th event shows the correction mechanism by fetching the two instructions again and yet again load D will be a speculative event because store C has not finished. The 7th event shows new value in location D and since it is cached and its value known, E[D] proceeds. The 8th event shows that store C has finished and since it does not effect D, the speculative value is correct and and is retired from the reorder and speculative-load buffers. The last even signifies the completion of E[D].<br />
<br />
== Future directions and ambitious implementations ==<br />
<br />
The paper by Adve and Hill <ref>[ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.pdf Implementing Sequential Consistency In Cache-Based Systems]</ref> proposes an implementation for sequential consistency that is more efficient than conventional implementations. Their scheme requires an invalidation-based cache coherence protocol. At points where a conventional implementation stalls for the full latency of pending writes, their implementation stalls only until ownership is gained. To make the implementation satisfy sequential consistency, the new value written is not made visible to other processors until all previous writes by this processor have completed. The gains from this are expected to be limited, however, since the latency of obtaining ownership is often only slightly smaller than the latency for the write to complete. In addition, the proposed scheme has no provision for hiding the latency of read accesses. Since the visibility-control mechanism reduces the stall time for writes only slightly and does not affect the stall time for reads, its performance wont be much better than conventional implementations. In contrast, the prefetch and speculative load techniques provide much greater opportunity for buffering and pipelining of read and write accesses.<br />
<br />
The paper by Stenstrom <ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 A latency-hiding scheme for multiprocessors with buffered multistage networks]</ref> proposes a mechanism for guaranteeing access order at the memory instead of at the processor. Each request contains a processor identification and a sequence number. Consecutive requests from the same processor get consecutive sequence numbers. Each memory module has access to a common data structure called next sequence-number table (NST). The NST contains P entries, one entry per processor. Each entry contains the sequence number of the next request to be performed by the corresponding processor. This allows the mechanism to guarantee that accesses from each processor are kept in program order. Theoretically, this scheme can enhance the performance of sequential consistency. However, the major disadvantage is that caches are not allowed. This can severely hinder the performance when compared to implementations that allow shared locations to be cached.<br />
<br />
To gain significant improvement in terms of performance, there have been a number of memory consistency models proposed. One disadvantage of the relaxed memory consistency models is that they present a more complex programming model to the user. The cost of this added performance benefit is however the extra hardware complexity that comes with it. The prefetch technique is simple and can easily be absorbed into the modern multi processor architectures while the speculative execution technique is not that easy when compared to the prefetch technique. Things get more complicated when the speculative execution technique is to be incorporated into multi processor systems when compared to uni processor systems. In future, we might expect better implementations of the speculative execution technique which will make this transition easy.<br />
<br />
== References ==<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/10a_vm&diff=61626CSC/ECE 506 Spring 2012/10a vm2012-04-06T14:42:39Z<p>Mbplautz: Section II</p>
<hr />
<div>Prefetching and consistency models.<br />
== Prefetching ==<br />
<br />
=== Introduction to prefetching ===<br />
<br />
Almost all processors today use [http://en.wikipedia.org/wiki/Instruction_prefetch prefetching] as a means to speed up execution. Primarily, prefetching is used to shorten the amount of time a processor is in the wait state by predicting which cache block would be accessed next, so that when a [http://en.wikipedia.org/wiki/CPU_cache#Cache_miss cache miss] occurs, the old block in the cache can be immediately replaced with the block that is prefetched and hence decreasing the idle time of the processor. Performance in prefetching is best when it is done by following the [http://en.wikipedia.org/wiki/Out-of-order_execution program order]. However, it need not always be that prefetching is done in program order; a processor trying to guess the result of a calculation during a complex [http://en.wikipedia.org/wiki/Branch_prediction branch prediction] algorithm will need to anticipate the result and fetch the right set of instructions for execution. Things get more complex when it comes to graphical processing units or GPUs. Prefetching can take advantage of [http://en.wikipedia.org/wiki/Coherence_(physics)#Spatial_coherence spatial coherence] and the data that is prefetched are not a set of instructions, but instead they are texture elements that can be mapped to a polygon.<ref>[http://en.wikipedia.org/wiki/Instruction_prefetch Instruction prefetch wiki article.]</ref><br />
<br />
=== Types of prefetching ===<br />
<br />
[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] can be primarily classified based on whether it is binding or non-binding, and whether it is hardware or software controlled. Using a binding prefetch, the value of a later reference, like a register load, is bound at the time the prefetch completes. However, this comes with added restrictions because the value in the prefetch might not be accurate - there might be invalidations that can be caused by another processor in the time frame between prefetch and reference by the current processor. Coming to the non-binding prefetch case, the data is stored into the processor cache, and the coherence is maintained till the processor reads or writes the value. This approach, unlike binding prefetch, will not have an effect on the correctness of any consistency model. It can serve as a serious improvement in terms of performance.<br />
<br />
The prefetch that is interesting to us is the hardware controlled and non-binding prefetch. Prefetching done in software involves significant effort from the programmer's side, and it may not be scalable as the length of the program increases. In comparison, the non-binding prefetch yields significantly more performance when compared to the binding prefetch. The major performance enhancement from prefetching comes by decreasing the memory latencies that are caused by all consistency models. <br />
<br />
In the case of a read operation, the read prefetch is issued to get the data in a read-only shared state in the cache. Since we are considering the non-binding prefetch, there is a guarantee that the read operation is going to return a correct value when it is allowed to run, irrespective of the actual prefetch completion time. However, there is also a catch to this: the value read might not always be correct. Consider a case where there is a write operation performed on the memory location that was just read-prefetched. Thus the value can be read again depending on whether an invalidation-based or an update-based coherence scheme is being used. If an [http://en.wikipedia.org/wiki/Cache_coherence update-based coherence scheme] is being used, we can be assured that the other processor will send a bus update and the current processor can pick it up to update its value. However, if an invalidation based coherence scheme is used, there would be a coherence miss and the value will be read again from the system memory, giving an illusion that the prefetch did not occur.<br />
<br />
In the case of a write operation, to acquire the exclusive ownership of the line, a read-exclusive prefetch can be used. Since it is cached in the exclusive mode, a write operation can proceed without incurring an invalidate or an update on other caches which have cached the same line or block. The write operation finishes quickly because the value is already cached and there is no coherence miss, thus reducing the idle time of the processor. However, it is to be noted that the read-exclusive prefetch is only possible if the coherence scheme is invalidation-based and not update-based. The same logic of incorrectness applies here that we have seen in the read case: suppose that another processor asks for a write to the same block; in this case, the exclusive ownership will no longer be maintained. Instead the cache block will be invalidated.<br />
<br />
=== How does prefetching work ? ===<br />
<br />
In a multiprocessor environment, each processor has a [http://en.wikipedia.org/wiki/Memory_disambiguation load] and a [http://en.wikipedia.org/wiki/Memory_disambiguation store buffer]. The way in which consistency models work are that the accesses to memory locations are delayed until the previous requests have finished. While issuing a read or a write request, we can implement the prefetch by making the hardware automatically issue a prefetch for requests which are in the load or store buffer and those requests which cannot be honored right away because of the delays incurred due to consistency model constraints. <br />
<br />
Let us trace through the steps a prefetch request would follow. First, it looks up the cache to see whether the block is already present. If it is indeed available, the request is terminated. If it is not present, the prefetch is issued to memory. Depending on the type of prefetch technique we are using, the response to the prefetch may or may not be immediate. The response is then placed in the cache. This process can be optimized by detecting duplicate requests to the same location and then combining the responses to each individual request to point to the prefetch request, thereby preventing duplicate requests being issued to memory. This mechanism also taxes the system in the form of requirements. Firstly, it requires that hardware coherent caches and the block that is prefetched should fit into the cache. Then for the write prefetch to work efficiently, there should be an invalidation-based coherence scheme in place. Additionally, the bus bandwidth should be high in order to handle several prefetch requests at the same time. The caches will also be more busy with read/write transactions when prefetching is implemented.<ref>[http://www.opensparc.net/pubs/papers/InstrPfHPCA05.pdf Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications]</ref> <br />
<br />
The amount of lookahead we do for a prefetch needs to be controlled, in the sense that if a higher number of blocks are prefetched than are required, then the processor might not ever use them and it would also result in increased cache misses of actually required blocks. Thus the extent to which lookahead is done should dynamically adjust depending on whether the processor actually uses the blocks or just evicts them without a read or a write reference to it.<br />
<br />
== Prefetching with Sequential Consistency ==<br />
<br />
Sequential Consistency (SC) might cause a reader to assume that its implementation will need a single memory module. However, this is not true. Both SC and the relaxed memory models allow many optimizations within them in order to deliver high performance. SC and the relaxed models allow non-binding prefetching along with coherent caching.<ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&sqi=2&ved=0CCkQFjAA&url=ftp%3A%2F%2Fftp.cs.wisc.edu%2Fpub%2Ftechreports%2F1991%2FTR1006.pdf&ei=cZ57T-j7DNCbtwenqIG1CA&usg=AFQjCNHtHiuYi2hYaVbTkSuELNg7PNQuXA&sig2=VFMR7Hq3ofiDnH8tzbFNUg Cache consistency and sequential consistency]</ref><br />
<br />
'''Let us take a look at an example and see how SC vs prefetching with SC performs'''<br />
<br />
The assumptions being made are that the processor has non-blocking reads with branch prediction machinery, an invalidation-based cache coherence scheme is in place, if there is a cache hit the latency is 1 clock cycle, and the cache miss incurs a latency of 100 clock cycles. <br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Since we are considering a system with SC, we know that an access to memory cannot be issued until the previous access has completed. The first three accesses are misses and they occur one after the other without any interleaving, which gives us a total latency of 100 x 3 = 300 clock cycles. The fourth operation however is a cache hit, thus adding only 1 clock cycle. The four accesses take up 301 clock cycles to complete.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance. Since the system has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
Comparing the 103 clock cycles in prefetching under SC .vs. SC only we see that there is nearly a 200 clock cycle difference, which is a significant improvement. As the number of accesses increase, the difference is only going to get larger until a certain point where "SC only" would no longer be a viable option.<br />
<br />
'''Another example showing how SC vs prefetching with SC performs'''<br />
<br />
The same assumptions are being made which we made for the first example.<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under SC only we see that the total number of clock cycles are 302.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching, we see that the total time taken will be 203 (2 misses & 3 hits).<br />
<br />
Thus again, we see that prefetching with SC performs better than "SC only".<br />
<br />
== Performance of prefetching with SC and why the idea has not been widely adopted ==<br />
<br />
We have seen two examples, where prefetching with SC does a better job than "SC only". But what we need to look at is whether this is the maximum performance which we can extract. Consider the second example where we had 3 reads in a critical section. The address which E[D] is trying to access will depend on the value of D. Read D was a cache hit, and E[D] is not allowed to perform under SC until the read C finishes. Thus, even though prefetching increases performance by reducing the time delay caused due to consistency constraints, it does not deal with situations where out of order usage of the values returned by memory access is critical for the processor to proceed efficiently. In other words, prefetching fails to do a good job when out of order consumption of values is important.<ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 Memory access dependencies in shared-memory multiprocessors]</ref><ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CDIQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.52.9935%26rep%3Drep1%26type%3Dpdf&ei=wp17T_vaKsrEtwe9yvSpCA&usg=AFQjCNGQXk84yrSUHkZU-mDw0D8KMVb6WQ&sig2=rhKqMuWKvTBHdFgK3rOthw Performance evaluation of memory consistency models for shared-memory multiprocessors]</ref><br />
<br />
Even though the main use of prefetching is to enable servicing of the requests faster when compared to the delay constraints imposed by the memory contraint models, correctness needs to be maintained at all times. The number of times a prefetched value is incorrect should be small, and luckily this is indeed true in real world systems for several reasons. The invalidation of the prefetched values is loosely coupled with the delay to obtain a correct execution sequence. These delays are imposed by the memory consistency models, and in SC which is the stricter of all models, imposes many delays. Usually, the time when one process releases a synchronization is much earlier when compared another process trying to acquire it. Thus the delays introduced by SC are unnecessary and therefore it taxes the systems performance. <ref>[http://dl.acm.org/citation.cfm?id=285991 Memory access buffering in multiprocessors]</ref><br />
<br />
Such cases are not rare to find in real applications and hence prefetching cannot be used all the time. Therefore prefetching under SC was not widely adopted and hence new schemes had to be developed in order to overcome the drawbacks of the current method.<br />
<br />
== Solution#1 Prefetching with Release Consistency ==<br />
<br />
Prefetching under release consistency does at least as good as prefetching under SC. Let us evaluate its performance in the two examples we looked at previously. We follow the same assumptions about the system which we have followed previously.<br />
<br />
'''The first example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Since we are considering a system with RC, we know that write accesses to memory are delayed until the lock access can be performed. The lock L operation takes 100 clock cycles to finish, followed by another 100+1 cycles for write A, write B to finish and then finally the fourth operation takes 1 clock cycle to finish because it is a hit. Thus the total number of clock cycles are 202 under the "RC only" approach.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance, atleast with SC. Since the system now has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
In this example, we found that prefetching with SC and prefetching with RC take the amount of time.<br />
<br />
'''The second example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under "RC only" we can see that the total number of clock cycles are 203.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we see that the total time taken will be 202 (2 misses & 2 hits pipelined).<br />
<br />
Thus again, we see that prefetching with RC performs better than "RC only".<br />
<br />
However, we have not got a significant performance gain in the second example. Thus even though RC allows more relaxation on the order of operations issued to memory, the gain is not much. Relaxed models offer more options on the hardware implementation perspective than SC, so we might get tempted to conclude that hardware must use the relaxed models instead of SC. On the other hand, the performance gain we expect too get is not being delivered under prefetching with RC, thus it cannot be justified to be a good approach either. Even though it performs better than prefetching under SC.<br />
<br />
Also, the same argument that we used for SC by mentioning that it taxes the system by causing unwanted delays to ensure correctness can be applied to the RC model as well. Though unlike SC, it may not tax the systems performance much, because in RC the delays are only inserted at synchronization points. Even then it forms a part of the argument that prefetching under RC is not a very good method.<br />
<br />
== Solution#2 Speculative Execution ==<br />
<br />
Speculative execution does impose many constraints which relaxed and SC implementations do, but rather it allows them to be more aggressive. Speculative execution allows the processor to execute instructions eagerly. However the same strictness when it comes to being correct applies. That is the instructions must be undone when speculations prove incorrect. This scenario can be found in wrongly predicted branches. When the processor knows that it cannot be wrong, it does a commit of the instruction which frees up the resources that were being used for implementation. There are two strict rules about instructions being committed: <ref>[http://en.wikipedia.org/wiki/Speculative_execution Speculative Execution wiki article]</ref><br />
<br />
- All instructions prior to the current instruction must be committed, &<br />
- The current instruction operation commits.<br />
<br />
For example, when we consider a load or store operation, we can be assured that it commits when it does a read or a write on a memory value. With speculative execution, both relaxed and SC implementations can perform operations out of order and in a speculative fashion. While comparing the peer performance of relaxed .vs. SC,<br />
<br />
read A (miss)<br />
read B (hit)<br />
<br />
When dealing with SC, read A occurs first, gets committed and then read B gets committed. However, with relaxed models, read B can get committed before read A gets committed. The difference in performance between relaxed and SC is very narrow. However, the measurement of the difference in performance depends upon benchmarks, latencies etc.<br />
<br />
The figure below shows an example implementation of a SE system.<ref>[http://www.csl.cornell.edu/courses/ee572/gharachorloo.icpp91.pdf Two Techniques to Enhance the Performance of Memory Consistency Models by Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]</ref><br />
<br />
[[File:SE_implementation.png|600px|Example implementation of a SE system. Source: Two Techniques to Enhance the Performance of Memory Consistency Models by<br />
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]]<br />
<br />
=== Idea behind speculative execution ===<br />
<br />
The core idea which forms the crux of speculative execution is simple and easy to understand. For example, let us consider there are two accesses a and b in the program order. a is considered to have a large latency whereas b is simply a load access. Also, the consistency model needs a to complete before b can finish. The speculative execution for load accesses proceeds as follows. The processor obtains the value returned by access b before a can complete and it proceeds. Now when a completes, the processor checks to see if the speculated return value of b before the completion of a is same as the actual value obtained after a completes. If they both match then the speculation was correct and the processor proceeds without any undo of instructions. However, if the values do not match then we need to redo access b to get the correct value <ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDUQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.57.1560%26rep%3Drep1%26type%3Dpdf&ei=lbB8T8DZKtKCtgeJ7v3mDA&usg=AFQjCNElr6qsvxH41INvR6tY12S4mDwLeQ&sig2=dk_gxOC4J7VEPz3I5EOgXA Speculative Execution in Real-Time Systems]</ref>. These steps in speculative execution can be summarized by 3 different mechanisms. Namely,<br />
<br />
a) The speculative mechanism<br />
b) The detection mechanism<br />
c) The correction mechanism<br />
<br />
'''a) The speculative mechanism -''' In the speculative mechanism, the most appropriate thing to do would be to perform the access, get the returned value and proceed to use the returned value. If there is a cache hit, the value will be returned instantly, else if it is a miss the access is pipelined with other accesses just like we have seen in prefetching.<br />
<br />
'''b) The detection mechanism -''' The way to detect if the speculated value is correct or not, is by redoing the access after the consistency model would have actually allowed it do be done without speculation. This however might not be the only way. If we could monitor the coherence transactions on that particular location in cache to see if there is an invalidation then the detection process can be faster. Thus another improvement when compared to the prefetch technique is that, in speculative execution the cache is only accessed once unlike twice which is the norm in prefetch technique. Going back to our example of two accesses a and b, the consistency model requires that access b is deferred until access a is complete. However, under the speculative execution, b can proceed without waiting for a to complete. The detection mechanism works by monitoring whether there is an update or invalidation at location b which is an indication that the speculation is incorrect. However, if there are no update or invalidation messages, we can be assured that the speculated value was correct.<br />
<br />
'''c) The correction mechanism -''' Once the detection mechanism determines that the speculated value is incorrect, the correction mechanism comes into play. The first step that the correction mechanism does is that it discards the computation of the speculated value. The load accesses and the computations after the speculated value can be discarded too, just like the correction mechanism used in processors when there is a branch prediction that has gone wrong.<br />
<br />
The figure below, shows the organization of a load/store functional unit of a SE system.<br />
<br />
[[File:Load_store.png|600px|Organization of a load store functional unit]]<br />
<br />
The speculative mechanism is superior to the prefetch mechanism (both under SC and RC) by giving an opportunity to use out of order speculated values.<br />
<br />
'''Referring back to the example we discussed while talking about performance of prefetching with RC/SC'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
The pipelining in both prefetching and speculative execution will be same and thus we might expect the same level of performance. But however read D does not cause a bottle neck because under speculative execution, its value can be immediately consumed before the previous accesses commit. Thus we expect both the SC and RC implementations to finish in 104 clock cycles (analogous to 4 hits and 1 miss).<br />
<br />
As soon as we know the address for the access, the load access can be issued under speculative execution irrespective of the consistency model that is being supported. Even speculative execution will impose requirements on the system. For all the three mechanisms discussed, we expect hardware support, else we might not get the performance gain that we expect if we implement the same in software.<ref>[http://impact.crhc.illinois.edu/ftp/conference/micro-93-suppression.pdf Speculative Execution Exception Recovery using Write-back Suppression]</ref><br />
<br />
=== Illustrative example ===<br />
<br />
This is the example which we will be taking up for discussion to see how SE works,<br />
<br />
[[File:SE_example.png|600px|Organization of a load store functional unit]]<br />
<br />
In the above figure, the contents of various buffers are showed along with the cache content for each event that occurs. All three mechanisms which we have discussed will be traced in the example. The reorder buffer holds the instructions that are fetched and decoded. Tracing through the set of events, initially the loads and prefetches (exclusive mode) are issued for the corresponding stores. In the meantime, while the store buffer is working on the store operations, the speculative load buffer has three loads. The returned value of read D has already been used by the processor. The second event indicates an ownership for B, however it is not immediately completed. Its completion has been reordered and delayed by the reorder buffer. The third event indicates that the value of A arrives and the entrees for A are purged from both the speculative-load and reorder buffers. Once the load A completes the reorder buffer signals the store buffer to allow the store B to complete. And this is a hit because the value is already cached and thus finishes quickly. Store C is next to be served in the reorder buffer and its access is merged with the previous prefetch request for the same location.<ref>[http://www.cs.waikato.ac.nz/timewarp/wengine/papers/gc99_1/ Data and Control Speculative Execution]</ref><br />
<br />
Now to make things interesting, let us assume that there is an invalidation for D. This would cause a mismatch in the value speculated for D and hence the load D and the instructions following it are purged, indicated by event 5. The 6th event shows the correction mechanism by fetching the two instructions again and yet again load D will be a speculative event because store C has not finished. The 7th event shows new value in location D and since it is cached and its value known, E[D] proceeds. The 8th event shows that store C has finished and since it does not effect D, the speculative value is correct and and is retired from the reorder and speculative-load buffers. The last even signifies the completion of E[D].<br />
<br />
== Future directions and ambitious implementations ==<br />
<br />
The paper by Adve and Hill <ref>[ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.pdf Implementing Sequential Consistency In Cache-Based Systems]</ref> proposes an implementation for sequential consistency that is more efficient than conventional implementations. Their scheme requires an invalidation-based cache coherence protocol. At points where a conventional implementation stalls for the full latency of pending writes, their implementation stalls only until ownership is gained. To make the implementation satisfy sequential consistency, the new value written is not made visible to other processors until all previous writes by this processor have completed. The gains from this are expected to be limited, however, since the latency of obtaining ownership is often only slightly smaller than the latency for the write to complete. In addition, the proposed scheme has no provision for hiding the latency of read accesses. Since the visibility-control mechanism reduces the stall time for writes only slightly and does not affect the stall time for reads, its performance wont be much better than conventional implementations. In contrast, the prefetch and speculative load techniques provide much greater opportunity for buffering and pipelining of read and write accesses.<br />
<br />
The paper by Stenstrom <ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 A latency-hiding scheme for multiprocessors with buffered multistage networks]</ref> proposes a mechanism for guaranteeing access order at the memory instead of at the processor. Each request contains a processor identification and a sequence number. Consecutive requests from the same processor get consecutive sequence numbers. Each memory module has access to a common data structure called next sequence-number table (NST). The NST contains P entries, one entry per processor. Each entry contains the sequence number of the next request to be performed by the corresponding processor. This allows the mechanism to guarantee that accesses from each processor are kept in program order. Theoretically, this scheme can enhance the performance of sequential consistency. However, the major disadvantage is that caches are not allowed. This can severely hinder the performance when compared to implementations that allow shared locations to be cached.<br />
<br />
To gain significant improvement in terms of performance, there have been a number of memory consistency models proposed. One disadvantage of the relaxed memory consistency models is that they present a more complex programming model to the user. The cost of this added performance benefit is however the extra hardware complexity that comes with it. The prefetch technique is simple and can easily be absorbed into the modern multi processor architectures while the speculative execution technique is not that easy when compared to the prefetch technique. Things get more complicated when the speculative execution technique is to be incorporated into multi processor systems when compared to uni processor systems. In future, we might expect better implementations of the speculative execution technique which will make this transition easy.<br />
<br />
== References ==<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/10a_vm&diff=61625CSC/ECE 506 Spring 2012/10a vm2012-04-06T14:36:46Z<p>Mbplautz: Section I-3</p>
<hr />
<div>Prefetching and consistency models.<br />
== Prefetching ==<br />
<br />
=== Introduction to prefetching ===<br />
<br />
Almost all processors today use [http://en.wikipedia.org/wiki/Instruction_prefetch prefetching] as a means to speed up execution. Primarily, prefetching is used to shorten the amount of time a processor is in the wait state by predicting which cache block would be accessed next, so that when a [http://en.wikipedia.org/wiki/CPU_cache#Cache_miss cache miss] occurs, the old block in the cache can be immediately replaced with the block that is prefetched and hence decreasing the idle time of the processor. Performance in prefetching is best when it is done by following the [http://en.wikipedia.org/wiki/Out-of-order_execution program order]. However, it need not always be that prefetching is done in program order; a processor trying to guess the result of a calculation during a complex [http://en.wikipedia.org/wiki/Branch_prediction branch prediction] algorithm will need to anticipate the result and fetch the right set of instructions for execution. Things get more complex when it comes to graphical processing units or GPUs. Prefetching can take advantage of [http://en.wikipedia.org/wiki/Coherence_(physics)#Spatial_coherence spatial coherence] and the data that is prefetched are not a set of instructions, but instead they are texture elements that can be mapped to a polygon.<ref>[http://en.wikipedia.org/wiki/Instruction_prefetch Instruction prefetch wiki article.]</ref><br />
<br />
=== Types of prefetching ===<br />
<br />
[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] can be primarily classified based on whether it is binding or non-binding, and whether it is hardware or software controlled. Using a binding prefetch, the value of a later reference, like a register load, is bound at the time the prefetch completes. However, this comes with added restrictions because the value in the prefetch might not be accurate - there might be invalidations that can be caused by another processor in the time frame between prefetch and reference by the current processor. Coming to the non-binding prefetch case, the data is stored into the processor cache, and the coherence is maintained till the processor reads or writes the value. This approach, unlike binding prefetch, will not have an effect on the correctness of any consistency model. It can serve as a serious improvement in terms of performance.<br />
<br />
The prefetch that is interesting to us is the hardware controlled and non-binding prefetch. Prefetching done in software involves significant effort from the programmer's side, and it may not be scalable as the length of the program increases. In comparison, the non-binding prefetch yields significantly more performance when compared to the binding prefetch. The major performance enhancement from prefetching comes by decreasing the memory latencies that are caused by all consistency models. <br />
<br />
In the case of a read operation, the read prefetch is issued to get the data in a read-only shared state in the cache. Since we are considering the non-binding prefetch, there is a guarantee that the read operation is going to return a correct value when it is allowed to run, irrespective of the actual prefetch completion time. However, there is also a catch to this: the value read might not always be correct. Consider a case where there is a write operation performed on the memory location that was just read-prefetched. Thus the value can be read again depending on whether an invalidation-based or an update-based coherence scheme is being used. If an [http://en.wikipedia.org/wiki/Cache_coherence update-based coherence scheme] is being used, we can be assured that the other processor will send a bus update and the current processor can pick it up to update its value. However, if an invalidation based coherence scheme is used, there would be a coherence miss and the value will be read again from the system memory, giving an illusion that the prefetch did not occur.<br />
<br />
In the case of a write operation, to acquire the exclusive ownership of the line, a read-exclusive prefetch can be used. Since it is cached in the exclusive mode, a write operation can proceed without incurring an invalidate or an update on other caches which have cached the same line or block. The write operation finishes quickly because the value is already cached and there is no coherence miss, thus reducing the idle time of the processor. However, it is to be noted that the read-exclusive prefetch is only possible if the coherence scheme is invalidation-based and not update-based. The same logic of incorrectness applies here that we have seen in the read case: suppose that another processor asks for a write to the same block; in this case, the exclusive ownership will no longer be maintained. Instead the cache block will be invalidated.<br />
<br />
=== How does prefetching work ? ===<br />
<br />
In a multiprocessor environment, each processor has a [http://en.wikipedia.org/wiki/Memory_disambiguation load] and a [http://en.wikipedia.org/wiki/Memory_disambiguation store buffer]. The way in which consistency models work are that the accesses to memory locations are delayed until the previous requests have finished. While issuing a read or a write request, we can implement the prefetch by making the hardware automatically issue a prefetch for requests which are in the load or store buffer and those requests which cannot be honored right away because of the delays incurred due to consistency model constraints. <br />
<br />
Let us trace through the steps a prefetch request would follow. First, it looks up the cache to see whether the block is already present. If it is indeed available, the request is terminated. If it is not present, the prefetch is issued to memory. Depending on the type of prefetch technique we are using, the response to the prefetch may or may not be immediate. The response is then placed in the cache. This process can be optimized by detecting duplicate requests to the same location and then combining the responses to each individual request to point to the prefetch request, thereby preventing duplicate requests being issued to memory. This mechanism also taxes the system in the form of requirements. Firstly, it requires that hardware coherent caches and the block that is prefetched should fit into the cache. Then for the write prefetch to work efficiently, there should be an invalidation-based coherence scheme in place. Additionally, the bus bandwidth should be high in order to handle several prefetch requests at the same time. The caches will also be more busy with read/write transactions when prefetching is implemented.<ref>[http://www.opensparc.net/pubs/papers/InstrPfHPCA05.pdf Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications]</ref> <br />
<br />
The amount of lookahead we do for a prefetch needs to be controlled, in the sense that if a higher number of blocks are prefetched than are required, then the processor might not ever use them and it would also result in increased cache misses of actually required blocks. Thus the extent to which lookahead is done should dynamically adjust depending on whether the processor actually uses the blocks or just evicts them without a read or a write reference to it.<br />
<br />
== Prefetching with Sequential Consistency ==<br />
<br />
Sequential Consistency (SC) might cause a reader to assume that its implementation will need a single memory module. However, this is not true. Both SC and the relaxed memory models allow many optimizations within them in order to deliver high performance. SC and the relaxed models allow non-binding prefetching along with coherent caching.<ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&sqi=2&ved=0CCkQFjAA&url=ftp%3A%2F%2Fftp.cs.wisc.edu%2Fpub%2Ftechreports%2F1991%2FTR1006.pdf&ei=cZ57T-j7DNCbtwenqIG1CA&usg=AFQjCNHtHiuYi2hYaVbTkSuELNg7PNQuXA&sig2=VFMR7Hq3ofiDnH8tzbFNUg Cache consistency and sequential consistency]</ref><br />
<br />
'''Let us take a look at an example and see how SC vs prefetching with SC performs'''<br />
<br />
Assumptions being made are that the processor has non-blocking reads with branch prediction machinery, an invalidation based cache coherence scheme is in place, if there is a cache hit the latency is 1 clock cycle and the cache miss incurs a latency of 100 clock cycles. <br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Since we are considering a system with SC, we know that an access to memory cannot be issued until the previous access has completed. The first three accesses are misses and they occur one after the other without any interleaving, which gives us a total latency of 100 x 3 = 300 clock cycles. The fourth operation however is a cache hit, thus adding only 1 clock cycle. The four accesses take up 301 clock cycles to complete.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance. Since the system has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
Comparing the 103 clock cycles in prefetching under SC .vs. SC only we see that there is nearly a 200 clock cycle difference which is a significant improvement. As the number of accesses increase, the difference is only going to get larger until a certain point where "SC only" would no longer be a viable option.<br />
<br />
'''Another example showing how SC vs prefetching with SC performs'''<br />
<br />
The same assumptions are being made which we made for the first example.<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under SC only we see that the total number of clock cycles are 302.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching, we see that the total time taken will be 203 (2 misses & 3 hits).<br />
<br />
Thus again, we see that prefetching with SC performs better than "SC only".<br />
<br />
== Performance of prefetching with SC and why the idea has not been widely adopted ==<br />
<br />
We have seen two examples, where prefetching with SC does a better job than "SC only". But what we need to look at is whether this is the maximum performance which we can extract. Consider the second example where we had 3 reads in a critical section. The address which E[D] is trying to access will depend on the value of D. Read D was a cache hit, and E[D] is not allowed to perform under SC until the read C finishes. Thus, even though prefetching increases performance by reducing the time delay caused due to consistency constraints, it does not deal with situations where out of order usage of the values returned by memory access is critical for the processor to proceed efficiently. In other words, prefetching fails to do a good job when out of order consumption of values is important.<ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 Memory access dependencies in shared-memory multiprocessors]</ref><ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CDIQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.52.9935%26rep%3Drep1%26type%3Dpdf&ei=wp17T_vaKsrEtwe9yvSpCA&usg=AFQjCNGQXk84yrSUHkZU-mDw0D8KMVb6WQ&sig2=rhKqMuWKvTBHdFgK3rOthw Performance evaluation of memory consistency models for shared-memory multiprocessors]</ref><br />
<br />
Even though the main use of prefetching is to enable servicing of the requests faster when compared to the delay constraints imposed by the memory contraint models, correctness needs to be maintained at all times. The number of times a prefetched value is incorrect should be small, and luckily this is indeed true in real world systems for several reasons. The invalidation of the prefetched values is loosely coupled with the delay to obtain a correct execution sequence. These delays are imposed by the memory consistency models, and in SC which is the stricter of all models, imposes many delays. Usually, the time when one process releases a synchronization is much earlier when compared another process trying to acquire it. Thus the delays introduced by SC are unnecessary and therefore it taxes the systems performance. <ref>[http://dl.acm.org/citation.cfm?id=285991 Memory access buffering in multiprocessors]</ref><br />
<br />
Such cases are not rare to find in real applications and hence prefetching cannot be used all the time. Therefore prefetching under SC was not widely adopted and hence new schemes had to be developed in order to overcome the drawbacks of the current method.<br />
<br />
== Solution#1 Prefetching with Release Consistency ==<br />
<br />
Prefetching under release consistency does at least as good as prefetching under SC. Let us evaluate its performance in the two examples we looked at previously. We follow the same assumptions about the system which we have followed previously.<br />
<br />
'''The first example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Since we are considering a system with RC, we know that write accesses to memory are delayed until the lock access can be performed. The lock L operation takes 100 clock cycles to finish, followed by another 100+1 cycles for write A, write B to finish and then finally the fourth operation takes 1 clock cycle to finish because it is a hit. Thus the total number of clock cycles are 202 under the "RC only" approach.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance, atleast with SC. Since the system now has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
In this example, we found that prefetching with SC and prefetching with RC take the amount of time.<br />
<br />
'''The second example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under "RC only" we can see that the total number of clock cycles are 203.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we see that the total time taken will be 202 (2 misses & 2 hits pipelined).<br />
<br />
Thus again, we see that prefetching with RC performs better than "RC only".<br />
<br />
However, we have not got a significant performance gain in the second example. Thus even though RC allows more relaxation on the order of operations issued to memory, the gain is not much. Relaxed models offer more options on the hardware implementation perspective than SC, so we might get tempted to conclude that hardware must use the relaxed models instead of SC. On the other hand, the performance gain we expect too get is not being delivered under prefetching with RC, thus it cannot be justified to be a good approach either. Even though it performs better than prefetching under SC.<br />
<br />
Also, the same argument that we used for SC by mentioning that it taxes the system by causing unwanted delays to ensure correctness can be applied to the RC model as well. Though unlike SC, it may not tax the systems performance much, because in RC the delays are only inserted at synchronization points. Even then it forms a part of the argument that prefetching under RC is not a very good method.<br />
<br />
== Solution#2 Speculative Execution ==<br />
<br />
Speculative execution does impose many constraints which relaxed and SC implementations do, but rather it allows them to be more aggressive. Speculative execution allows the processor to execute instructions eagerly. However the same strictness when it comes to being correct applies. That is the instructions must be undone when speculations prove incorrect. This scenario can be found in wrongly predicted branches. When the processor knows that it cannot be wrong, it does a commit of the instruction which frees up the resources that were being used for implementation. There are two strict rules about instructions being committed: <ref>[http://en.wikipedia.org/wiki/Speculative_execution Speculative Execution wiki article]</ref><br />
<br />
- All instructions prior to the current instruction must be committed, &<br />
- The current instruction operation commits.<br />
<br />
For example, when we consider a load or store operation, we can be assured that it commits when it does a read or a write on a memory value. With speculative execution, both relaxed and SC implementations can perform operations out of order and in a speculative fashion. While comparing the peer performance of relaxed .vs. SC,<br />
<br />
read A (miss)<br />
read B (hit)<br />
<br />
When dealing with SC, read A occurs first, gets committed and then read B gets committed. However, with relaxed models, read B can get committed before read A gets committed. The difference in performance between relaxed and SC is very narrow. However, the measurement of the difference in performance depends upon benchmarks, latencies etc.<br />
<br />
The figure below shows an example implementation of a SE system.<ref>[http://www.csl.cornell.edu/courses/ee572/gharachorloo.icpp91.pdf Two Techniques to Enhance the Performance of Memory Consistency Models by Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]</ref><br />
<br />
[[File:SE_implementation.png|600px|Example implementation of a SE system. Source: Two Techniques to Enhance the Performance of Memory Consistency Models by<br />
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]]<br />
<br />
=== Idea behind speculative execution ===<br />
<br />
The core idea which forms the crux of speculative execution is simple and easy to understand. For example, let us consider there are two accesses a and b in the program order. a is considered to have a large latency whereas b is simply a load access. Also, the consistency model needs a to complete before b can finish. The speculative execution for load accesses proceeds as follows. The processor obtains the value returned by access b before a can complete and it proceeds. Now when a completes, the processor checks to see if the speculated return value of b before the completion of a is same as the actual value obtained after a completes. If they both match then the speculation was correct and the processor proceeds without any undo of instructions. However, if the values do not match then we need to redo access b to get the correct value <ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDUQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.57.1560%26rep%3Drep1%26type%3Dpdf&ei=lbB8T8DZKtKCtgeJ7v3mDA&usg=AFQjCNElr6qsvxH41INvR6tY12S4mDwLeQ&sig2=dk_gxOC4J7VEPz3I5EOgXA Speculative Execution in Real-Time Systems]</ref>. These steps in speculative execution can be summarized by 3 different mechanisms. Namely,<br />
<br />
a) The speculative mechanism<br />
b) The detection mechanism<br />
c) The correction mechanism<br />
<br />
'''a) The speculative mechanism -''' In the speculative mechanism, the most appropriate thing to do would be to perform the access, get the returned value and proceed to use the returned value. If there is a cache hit, the value will be returned instantly, else if it is a miss the access is pipelined with other accesses just like we have seen in prefetching.<br />
<br />
'''b) The detection mechanism -''' The way to detect if the speculated value is correct or not, is by redoing the access after the consistency model would have actually allowed it do be done without speculation. This however might not be the only way. If we could monitor the coherence transactions on that particular location in cache to see if there is an invalidation then the detection process can be faster. Thus another improvement when compared to the prefetch technique is that, in speculative execution the cache is only accessed once unlike twice which is the norm in prefetch technique. Going back to our example of two accesses a and b, the consistency model requires that access b is deferred until access a is complete. However, under the speculative execution, b can proceed without waiting for a to complete. The detection mechanism works by monitoring whether there is an update or invalidation at location b which is an indication that the speculation is incorrect. However, if there are no update or invalidation messages, we can be assured that the speculated value was correct.<br />
<br />
'''c) The correction mechanism -''' Once the detection mechanism determines that the speculated value is incorrect, the correction mechanism comes into play. The first step that the correction mechanism does is that it discards the computation of the speculated value. The load accesses and the computations after the speculated value can be discarded too, just like the correction mechanism used in processors when there is a branch prediction that has gone wrong.<br />
<br />
The figure below, shows the organization of a load/store functional unit of a SE system.<br />
<br />
[[File:Load_store.png|600px|Organization of a load store functional unit]]<br />
<br />
The speculative mechanism is superior to the prefetch mechanism (both under SC and RC) by giving an opportunity to use out of order speculated values.<br />
<br />
'''Referring back to the example we discussed while talking about performance of prefetching with RC/SC'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
The pipelining in both prefetching and speculative execution will be same and thus we might expect the same level of performance. But however read D does not cause a bottle neck because under speculative execution, its value can be immediately consumed before the previous accesses commit. Thus we expect both the SC and RC implementations to finish in 104 clock cycles (analogous to 4 hits and 1 miss).<br />
<br />
As soon as we know the address for the access, the load access can be issued under speculative execution irrespective of the consistency model that is being supported. Even speculative execution will impose requirements on the system. For all the three mechanisms discussed, we expect hardware support, else we might not get the performance gain that we expect if we implement the same in software.<ref>[http://impact.crhc.illinois.edu/ftp/conference/micro-93-suppression.pdf Speculative Execution Exception Recovery using Write-back Suppression]</ref><br />
<br />
=== Illustrative example ===<br />
<br />
This is the example which we will be taking up for discussion to see how SE works,<br />
<br />
[[File:SE_example.png|600px|Organization of a load store functional unit]]<br />
<br />
In the above figure, the contents of various buffers are showed along with the cache content for each event that occurs. All three mechanisms which we have discussed will be traced in the example. The reorder buffer holds the instructions that are fetched and decoded. Tracing through the set of events, initially the loads and prefetches (exclusive mode) are issued for the corresponding stores. In the meantime, while the store buffer is working on the store operations, the speculative load buffer has three loads. The returned value of read D has already been used by the processor. The second event indicates an ownership for B, however it is not immediately completed. Its completion has been reordered and delayed by the reorder buffer. The third event indicates that the value of A arrives and the entrees for A are purged from both the speculative-load and reorder buffers. Once the load A completes the reorder buffer signals the store buffer to allow the store B to complete. And this is a hit because the value is already cached and thus finishes quickly. Store C is next to be served in the reorder buffer and its access is merged with the previous prefetch request for the same location.<ref>[http://www.cs.waikato.ac.nz/timewarp/wengine/papers/gc99_1/ Data and Control Speculative Execution]</ref><br />
<br />
Now to make things interesting, let us assume that there is an invalidation for D. This would cause a mismatch in the value speculated for D and hence the load D and the instructions following it are purged, indicated by event 5. The 6th event shows the correction mechanism by fetching the two instructions again and yet again load D will be a speculative event because store C has not finished. The 7th event shows new value in location D and since it is cached and its value known, E[D] proceeds. The 8th event shows that store C has finished and since it does not effect D, the speculative value is correct and and is retired from the reorder and speculative-load buffers. The last even signifies the completion of E[D].<br />
<br />
== Future directions and ambitious implementations ==<br />
<br />
The paper by Adve and Hill <ref>[ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.pdf Implementing Sequential Consistency In Cache-Based Systems]</ref> proposes an implementation for sequential consistency that is more efficient than conventional implementations. Their scheme requires an invalidation-based cache coherence protocol. At points where a conventional implementation stalls for the full latency of pending writes, their implementation stalls only until ownership is gained. To make the implementation satisfy sequential consistency, the new value written is not made visible to other processors until all previous writes by this processor have completed. The gains from this are expected to be limited, however, since the latency of obtaining ownership is often only slightly smaller than the latency for the write to complete. In addition, the proposed scheme has no provision for hiding the latency of read accesses. Since the visibility-control mechanism reduces the stall time for writes only slightly and does not affect the stall time for reads, its performance wont be much better than conventional implementations. In contrast, the prefetch and speculative load techniques provide much greater opportunity for buffering and pipelining of read and write accesses.<br />
<br />
The paper by Stenstrom <ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 A latency-hiding scheme for multiprocessors with buffered multistage networks]</ref> proposes a mechanism for guaranteeing access order at the memory instead of at the processor. Each request contains a processor identification and a sequence number. Consecutive requests from the same processor get consecutive sequence numbers. Each memory module has access to a common data structure called next sequence-number table (NST). The NST contains P entries, one entry per processor. Each entry contains the sequence number of the next request to be performed by the corresponding processor. This allows the mechanism to guarantee that accesses from each processor are kept in program order. Theoretically, this scheme can enhance the performance of sequential consistency. However, the major disadvantage is that caches are not allowed. This can severely hinder the performance when compared to implementations that allow shared locations to be cached.<br />
<br />
To gain significant improvement in terms of performance, there have been a number of memory consistency models proposed. One disadvantage of the relaxed memory consistency models is that they present a more complex programming model to the user. The cost of this added performance benefit is however the extra hardware complexity that comes with it. The prefetch technique is simple and can easily be absorbed into the modern multi processor architectures while the speculative execution technique is not that easy when compared to the prefetch technique. Things get more complicated when the speculative execution technique is to be incorporated into multi processor systems when compared to uni processor systems. In future, we might expect better implementations of the speculative execution technique which will make this transition easy.<br />
<br />
== References ==<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/10a_vm&diff=61624CSC/ECE 506 Spring 2012/10a vm2012-04-06T14:08:14Z<p>Mbplautz: Grammer, section I-1 and I-2</p>
<hr />
<div>Prefetching and consistency models.<br />
== Prefetching ==<br />
<br />
=== Introduction to prefetching ===<br />
<br />
Almost all processors today use [http://en.wikipedia.org/wiki/Instruction_prefetch prefetching] as a means to speed up execution. Primarily, prefetching is used to shorten the amount of time a processor is in the wait state by predicting which cache block would be accessed next, so that when a [http://en.wikipedia.org/wiki/CPU_cache#Cache_miss cache miss] occurs, the old block in the cache can be immediately replaced with the block that is prefetched and hence decreasing the idle time of the processor. Performance in prefetching is best when it is done by following the [http://en.wikipedia.org/wiki/Out-of-order_execution program order]. However, it need not always be that prefetching is done in program order; a processor trying to guess the result of a calculation during a complex [http://en.wikipedia.org/wiki/Branch_prediction branch prediction] algorithm will need to anticipate the result and fetch the right set of instructions for execution. Things get more complex when it comes to graphical processing units or GPUs. Prefetching can take advantage of [http://en.wikipedia.org/wiki/Coherence_(physics)#Spatial_coherence spatial coherence] and the data that is prefetched are not a set of instructions, but instead they are texture elements that can be mapped to a polygon.<ref>[http://en.wikipedia.org/wiki/Instruction_prefetch Instruction prefetch wiki article.]</ref><br />
<br />
=== Types of prefetching ===<br />
<br />
[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] can be primarily classified based on whether it is binding or non-binding, and whether it is hardware or software controlled. Using a binding prefetch, the value of a later reference, like a register load, is bound at the time the prefetch completes. However, this comes with added restrictions because the value in the prefetch might not be accurate - there might be invalidations that can be caused by another processor in the time frame between prefetch and reference by the current processor. Coming to the non-binding prefetch case, the data is stored into the processor cache, and the coherence is maintained till the processor reads or writes the value. This approach, unlike binding prefetch, will not have an effect on the correctness of any consistency model. It can serve as a serious improvement in terms of performance.<br />
<br />
The prefetch that is interesting to us is the hardware controlled and non-binding prefetch. Prefetching done in software involves significant effort from the programmer's side, and it may not be scalable as the length of the program increases. In comparison, the non-binding prefetch yields significantly more performance when compared to the binding prefetch. The major performance enhancement from prefetching comes by decreasing the memory latencies that are caused by all consistency models. <br />
<br />
In the case of a read operation, the read prefetch is issued to get the data in a read-only shared state in the cache. Since we are considering the non-binding prefetch, there is a guarantee that the read operation is going to return a correct value when it is allowed to run, irrespective of the actual prefetch completion time. However, there is also a catch to this: the value read might not always be correct. Consider a case where there is a write operation performed on the memory location that was just read-prefetched. Thus the value can be read again depending on whether an invalidation-based or an update-based coherence scheme is being used. If an [http://en.wikipedia.org/wiki/Cache_coherence update-based coherence scheme] is being used, we can be assured that the other processor will send a bus update and the current processor can pick it up to update its value. However, if an invalidation based coherence scheme is used, there would be a coherence miss and the value will be read again from the system memory, giving an illusion that the prefetch did not occur.<br />
<br />
In the case of a write operation, to acquire the exclusive ownership of the line, a read-exclusive prefetch can be used. Since it is cached in the exclusive mode, a write operation can proceed without incurring an invalidate or an update on other caches which have cached the same line or block. The write operation finishes quickly because the value is already cached and there is no coherence miss, thus reducing the idle time of the processor. However, it is to be noted that the read-exclusive prefetch is only possible if the coherence scheme is invalidation-based and not update-based. The same logic of incorrectness applies here that we have seen in the read case: suppose that another processor asks for a write to the same block; in this case, the exclusive ownership will no longer be maintained. Instead the cache block will be invalidated.<br />
<br />
=== How does prefetching work ? ===<br />
<br />
In a multiprocessor environment, each processor has a [http://en.wikipedia.org/wiki/Memory_disambiguation load] and a [http://en.wikipedia.org/wiki/Memory_disambiguation store buffer]. The way in which consistency models work are that the accesses to memory locations are delayed until the previous requests have finished. While issuing a read or a write request, we can implement the prefetch by making the hardware automatically issue a prefetch for requests which are in the load or store buffer and those requests which cannot be honored right away because of the delays incurred due to consistency model constraints. <br />
<br />
Let us trace through the steps a prefetch request would follow. First it looks up the cache to see whether the block is already present. If it is indeed available, the request is terminated. If it is not present, the prefetch is issued to memory. Depending on the type of prefetch technique we are using, the response to the prefetch might be immediate or not. The response is then placed in the cache. This process can be optimized by detecting duplicate requests to the same location and then combining the responses to each individual request to point to the prefetch request, thereby preventing duplicate requests being issued to memory. This mechanism also taxes the system in the form of requirements. Firstly, it requires hardware coherent caches and the the block that is prefetched should fit into the cache. Then for the write prefetch to work efficiently, there should be an invalidation based coherence scheme in place. Not only these, the bus bandwidth should be high in order to handle several prefetch requests at the same time. The caches will also be more busy with read write transactions when prefetching is implemented.<ref>[http://www.opensparc.net/pubs/papers/InstrPfHPCA05.pdf Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications]</ref> <br />
<br />
The amount of lookahead we do for a prefetch needs to be controlled, in the sense that if more number of blocks are prefetched than required, then the processor might not ever use it and it would also result in increased cache misses of actually required blocks. Thus the extent to which lookahead is done should dynamically adjust depending on whether the processor actually uses the blocks or just evicts them without a read or a write reference to it.<br />
<br />
== Prefetching with Sequential Consistency ==<br />
<br />
Sequential Consistency (SC) might cause a reader to assume that its implementation will need a single memory module. However, this is not true. Both SC and the relaxed memory models allow many optimizations within them in order to deliver high performance. SC and the relaxed models allow non-binding prefetching along with coherent caching.<ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&sqi=2&ved=0CCkQFjAA&url=ftp%3A%2F%2Fftp.cs.wisc.edu%2Fpub%2Ftechreports%2F1991%2FTR1006.pdf&ei=cZ57T-j7DNCbtwenqIG1CA&usg=AFQjCNHtHiuYi2hYaVbTkSuELNg7PNQuXA&sig2=VFMR7Hq3ofiDnH8tzbFNUg Cache consistency and sequential consistency]</ref><br />
<br />
'''Let us take a look at an example and see how SC vs prefetching with SC performs'''<br />
<br />
Assumptions being made are that the processor has non-blocking reads with branch prediction machinery, an invalidation based cache coherence scheme is in place, if there is a cache hit the latency is 1 clock cycle and the cache miss incurs a latency of 100 clock cycles. <br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Since we are considering a system with SC, we know that an access to memory cannot be issued until the previous access has completed. The first three accesses are misses and they occur one after the other without any interleaving, which gives us a total latency of 100 x 3 = 300 clock cycles. The fourth operation however is a cache hit, thus adding only 1 clock cycle. The four accesses take up 301 clock cycles to complete.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance. Since the system has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
Comparing the 103 clock cycles in prefetching under SC .vs. SC only we see that there is nearly a 200 clock cycle difference which is a significant improvement. As the number of accesses increase, the difference is only going to get larger until a certain point where "SC only" would no longer be a viable option.<br />
<br />
'''Another example showing how SC vs prefetching with SC performs'''<br />
<br />
The same assumptions are being made which we made for the first example.<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under SC only we see that the total number of clock cycles are 302.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching, we see that the total time taken will be 203 (2 misses & 3 hits).<br />
<br />
Thus again, we see that prefetching with SC performs better than "SC only".<br />
<br />
== Performance of prefetching with SC and why the idea has not been widely adopted ==<br />
<br />
We have seen two examples, where prefetching with SC does a better job than "SC only". But what we need to look at is whether this is the maximum performance which we can extract. Consider the second example where we had 3 reads in a critical section. The address which E[D] is trying to access will depend on the value of D. Read D was a cache hit, and E[D] is not allowed to perform under SC until the read C finishes. Thus, even though prefetching increases performance by reducing the time delay caused due to consistency constraints, it does not deal with situations where out of order usage of the values returned by memory access is critical for the processor to proceed efficiently. In other words, prefetching fails to do a good job when out of order consumption of values is important.<ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 Memory access dependencies in shared-memory multiprocessors]</ref><ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CDIQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.52.9935%26rep%3Drep1%26type%3Dpdf&ei=wp17T_vaKsrEtwe9yvSpCA&usg=AFQjCNGQXk84yrSUHkZU-mDw0D8KMVb6WQ&sig2=rhKqMuWKvTBHdFgK3rOthw Performance evaluation of memory consistency models for shared-memory multiprocessors]</ref><br />
<br />
Even though the main use of prefetching is to enable servicing of the requests faster when compared to the delay constraints imposed by the memory contraint models, correctness needs to be maintained at all times. The number of times a prefetched value is incorrect should be small, and luckily this is indeed true in real world systems for several reasons. The invalidation of the prefetched values is loosely coupled with the delay to obtain a correct execution sequence. These delays are imposed by the memory consistency models, and in SC which is the stricter of all models, imposes many delays. Usually, the time when one process releases a synchronization is much earlier when compared another process trying to acquire it. Thus the delays introduced by SC are unnecessary and therefore it taxes the systems performance. <ref>[http://dl.acm.org/citation.cfm?id=285991 Memory access buffering in multiprocessors]</ref><br />
<br />
Such cases are not rare to find in real applications and hence prefetching cannot be used all the time. Therefore prefetching under SC was not widely adopted and hence new schemes had to be developed in order to overcome the drawbacks of the current method.<br />
<br />
== Solution#1 Prefetching with Release Consistency ==<br />
<br />
Prefetching under release consistency does at least as good as prefetching under SC. Let us evaluate its performance in the two examples we looked at previously. We follow the same assumptions about the system which we have followed previously.<br />
<br />
'''The first example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Since we are considering a system with RC, we know that write accesses to memory are delayed until the lock access can be performed. The lock L operation takes 100 clock cycles to finish, followed by another 100+1 cycles for write A, write B to finish and then finally the fourth operation takes 1 clock cycle to finish because it is a hit. Thus the total number of clock cycles are 202 under the "RC only" approach.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance, atleast with SC. Since the system now has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
In this example, we found that prefetching with SC and prefetching with RC take the amount of time.<br />
<br />
'''The second example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under "RC only" we can see that the total number of clock cycles are 203.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we see that the total time taken will be 202 (2 misses & 2 hits pipelined).<br />
<br />
Thus again, we see that prefetching with RC performs better than "RC only".<br />
<br />
However, we have not got a significant performance gain in the second example. Thus even though RC allows more relaxation on the order of operations issued to memory, the gain is not much. Relaxed models offer more options on the hardware implementation perspective than SC, so we might get tempted to conclude that hardware must use the relaxed models instead of SC. On the other hand, the performance gain we expect too get is not being delivered under prefetching with RC, thus it cannot be justified to be a good approach either. Even though it performs better than prefetching under SC.<br />
<br />
Also, the same argument that we used for SC by mentioning that it taxes the system by causing unwanted delays to ensure correctness can be applied to the RC model as well. Though unlike SC, it may not tax the systems performance much, because in RC the delays are only inserted at synchronization points. Even then it forms a part of the argument that prefetching under RC is not a very good method.<br />
<br />
== Solution#2 Speculative Execution ==<br />
<br />
Speculative execution does impose many constraints which relaxed and SC implementations do, but rather it allows them to be more aggressive. Speculative execution allows the processor to execute instructions eagerly. However the same strictness when it comes to being correct applies. That is the instructions must be undone when speculations prove incorrect. This scenario can be found in wrongly predicted branches. When the processor knows that it cannot be wrong, it does a commit of the instruction which frees up the resources that were being used for implementation. There are two strict rules about instructions being committed: <ref>[http://en.wikipedia.org/wiki/Speculative_execution Speculative Execution wiki article]</ref><br />
<br />
- All instructions prior to the current instruction must be committed, &<br />
- The current instruction operation commits.<br />
<br />
For example, when we consider a load or store operation, we can be assured that it commits when it does a read or a write on a memory value. With speculative execution, both relaxed and SC implementations can perform operations out of order and in a speculative fashion. While comparing the peer performance of relaxed .vs. SC,<br />
<br />
read A (miss)<br />
read B (hit)<br />
<br />
When dealing with SC, read A occurs first, gets committed and then read B gets committed. However, with relaxed models, read B can get committed before read A gets committed. The difference in performance between relaxed and SC is very narrow. However, the measurement of the difference in performance depends upon benchmarks, latencies etc.<br />
<br />
The figure below shows an example implementation of a SE system.<ref>[http://www.csl.cornell.edu/courses/ee572/gharachorloo.icpp91.pdf Two Techniques to Enhance the Performance of Memory Consistency Models by Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]</ref><br />
<br />
[[File:SE_implementation.png|600px|Example implementation of a SE system. Source: Two Techniques to Enhance the Performance of Memory Consistency Models by<br />
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]]<br />
<br />
=== Idea behind speculative execution ===<br />
<br />
The core idea which forms the crux of speculative execution is simple and easy to understand. For example, let us consider there are two accesses a and b in the program order. a is considered to have a large latency whereas b is simply a load access. Also, the consistency model needs a to complete before b can finish. The speculative execution for load accesses proceeds as follows. The processor obtains the value returned by access b before a can complete and it proceeds. Now when a completes, the processor checks to see if the speculated return value of b before the completion of a is same as the actual value obtained after a completes. If they both match then the speculation was correct and the processor proceeds without any undo of instructions. However, if the values do not match then we need to redo access b to get the correct value <ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDUQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.57.1560%26rep%3Drep1%26type%3Dpdf&ei=lbB8T8DZKtKCtgeJ7v3mDA&usg=AFQjCNElr6qsvxH41INvR6tY12S4mDwLeQ&sig2=dk_gxOC4J7VEPz3I5EOgXA Speculative Execution in Real-Time Systems]</ref>. These steps in speculative execution can be summarized by 3 different mechanisms. Namely,<br />
<br />
a) The speculative mechanism<br />
b) The detection mechanism<br />
c) The correction mechanism<br />
<br />
'''a) The speculative mechanism -''' In the speculative mechanism, the most appropriate thing to do would be to perform the access, get the returned value and proceed to use the returned value. If there is a cache hit, the value will be returned instantly, else if it is a miss the access is pipelined with other accesses just like we have seen in prefetching.<br />
<br />
'''b) The detection mechanism -''' The way to detect if the speculated value is correct or not, is by redoing the access after the consistency model would have actually allowed it do be done without speculation. This however might not be the only way. If we could monitor the coherence transactions on that particular location in cache to see if there is an invalidation then the detection process can be faster. Thus another improvement when compared to the prefetch technique is that, in speculative execution the cache is only accessed once unlike twice which is the norm in prefetch technique. Going back to our example of two accesses a and b, the consistency model requires that access b is deferred until access a is complete. However, under the speculative execution, b can proceed without waiting for a to complete. The detection mechanism works by monitoring whether there is an update or invalidation at location b which is an indication that the speculation is incorrect. However, if there are no update or invalidation messages, we can be assured that the speculated value was correct.<br />
<br />
'''c) The correction mechanism -''' Once the detection mechanism determines that the speculated value is incorrect, the correction mechanism comes into play. The first step that the correction mechanism does is that it discards the computation of the speculated value. The load accesses and the computations after the speculated value can be discarded too, just like the correction mechanism used in processors when there is a branch prediction that has gone wrong.<br />
<br />
The figure below, shows the organization of a load/store functional unit of a SE system.<br />
<br />
[[File:Load_store.png|600px|Organization of a load store functional unit]]<br />
<br />
The speculative mechanism is superior to the prefetch mechanism (both under SC and RC) by giving an opportunity to use out of order speculated values.<br />
<br />
'''Referring back to the example we discussed while talking about performance of prefetching with RC/SC'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
The pipelining in both prefetching and speculative execution will be same and thus we might expect the same level of performance. But however read D does not cause a bottle neck because under speculative execution, its value can be immediately consumed before the previous accesses commit. Thus we expect both the SC and RC implementations to finish in 104 clock cycles (analogous to 4 hits and 1 miss).<br />
<br />
As soon as we know the address for the access, the load access can be issued under speculative execution irrespective of the consistency model that is being supported. Even speculative execution will impose requirements on the system. For all the three mechanisms discussed, we expect hardware support, else we might not get the performance gain that we expect if we implement the same in software.<ref>[http://impact.crhc.illinois.edu/ftp/conference/micro-93-suppression.pdf Speculative Execution Exception Recovery using Write-back Suppression]</ref><br />
<br />
=== Illustrative example ===<br />
<br />
This is the example which we will be taking up for discussion to see how SE works,<br />
<br />
[[File:SE_example.png|600px|Organization of a load store functional unit]]<br />
<br />
In the above figure, the contents of various buffers are showed along with the cache content for each event that occurs. All three mechanisms which we have discussed will be traced in the example. The reorder buffer holds the instructions that are fetched and decoded. Tracing through the set of events, initially the loads and prefetches (exclusive mode) are issued for the corresponding stores. In the meantime, while the store buffer is working on the store operations, the speculative load buffer has three loads. The returned value of read D has already been used by the processor. The second event indicates an ownership for B, however it is not immediately completed. Its completion has been reordered and delayed by the reorder buffer. The third event indicates that the value of A arrives and the entrees for A are purged from both the speculative-load and reorder buffers. Once the load A completes the reorder buffer signals the store buffer to allow the store B to complete. And this is a hit because the value is already cached and thus finishes quickly. Store C is next to be served in the reorder buffer and its access is merged with the previous prefetch request for the same location.<ref>[http://www.cs.waikato.ac.nz/timewarp/wengine/papers/gc99_1/ Data and Control Speculative Execution]</ref><br />
<br />
Now to make things interesting, let us assume that there is an invalidation for D. This would cause a mismatch in the value speculated for D and hence the load D and the instructions following it are purged, indicated by event 5. The 6th event shows the correction mechanism by fetching the two instructions again and yet again load D will be a speculative event because store C has not finished. The 7th event shows new value in location D and since it is cached and its value known, E[D] proceeds. The 8th event shows that store C has finished and since it does not effect D, the speculative value is correct and and is retired from the reorder and speculative-load buffers. The last even signifies the completion of E[D].<br />
<br />
== Future directions and ambitious implementations ==<br />
<br />
The paper by Adve and Hill <ref>[ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.pdf Implementing Sequential Consistency In Cache-Based Systems]</ref> proposes an implementation for sequential consistency that is more efficient than conventional implementations. Their scheme requires an invalidation-based cache coherence protocol. At points where a conventional implementation stalls for the full latency of pending writes, their implementation stalls only until ownership is gained. To make the implementation satisfy sequential consistency, the new value written is not made visible to other processors until all previous writes by this processor have completed. The gains from this are expected to be limited, however, since the latency of obtaining ownership is often only slightly smaller than the latency for the write to complete. In addition, the proposed scheme has no provision for hiding the latency of read accesses. Since the visibility-control mechanism reduces the stall time for writes only slightly and does not affect the stall time for reads, its performance wont be much better than conventional implementations. In contrast, the prefetch and speculative load techniques provide much greater opportunity for buffering and pipelining of read and write accesses.<br />
<br />
The paper by Stenstrom <ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 A latency-hiding scheme for multiprocessors with buffered multistage networks]</ref> proposes a mechanism for guaranteeing access order at the memory instead of at the processor. Each request contains a processor identification and a sequence number. Consecutive requests from the same processor get consecutive sequence numbers. Each memory module has access to a common data structure called next sequence-number table (NST). The NST contains P entries, one entry per processor. Each entry contains the sequence number of the next request to be performed by the corresponding processor. This allows the mechanism to guarantee that accesses from each processor are kept in program order. Theoretically, this scheme can enhance the performance of sequential consistency. However, the major disadvantage is that caches are not allowed. This can severely hinder the performance when compared to implementations that allow shared locations to be cached.<br />
<br />
To gain significant improvement in terms of performance, there have been a number of memory consistency models proposed. One disadvantage of the relaxed memory consistency models is that they present a more complex programming model to the user. The cost of this added performance benefit is however the extra hardware complexity that comes with it. The prefetch technique is simple and can easily be absorbed into the modern multi processor architectures while the speculative execution technique is not that easy when compared to the prefetch technique. Things get more complicated when the speculative execution technique is to be incorporated into multi processor systems when compared to uni processor systems. In future, we might expect better implementations of the speculative execution technique which will make this transition easy.<br />
<br />
== References ==<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/10a_vm&diff=61585CSC/ECE 506 Spring 2012/10a vm2012-04-06T02:09:24Z<p>Mbplautz: </p>
<hr />
<div>Prefetching and consistency models.<br />
== Prefetching ==<br />
<br />
=== Introduction to prefetching ===<br />
<br />
Almost all processors today use [http://en.wikipedia.org/wiki/Instruction_prefetch prefetching] as a means to speed up execution. Primarily, prefetching is used to shorten the amount of time a processor is in the wait state by predicting which cache block would be accessed next, so that when a [http://en.wikipedia.org/wiki/CPU_cache#Cache_miss cache miss] occurs, the old block in the cache can be immediately replaced with the block that is prefetched and hence decreasing the idle time of the processor. Performance in prefetching is best when it is done by following the [http://en.wikipedia.org/wiki/Out-of-order_execution program order]. However, it need not always be that prefetching is done in program order; a processor trying to guess the result of a calculation during a complex [http://en.wikipedia.org/wiki/Branch_prediction branch prediction] algorithm will need to anticipate the result and fetch the right set of instructions for execution. Things get more complex when it comes to graphical processing units or GPUs. Prefetching can take advantage of [http://en.wikipedia.org/wiki/Coherence_(physics)#Spatial_coherence spatial coherence] and the data that is prefetched are not a set of instructions, but instead they are texture elements that can be mapped to a polygon.<ref>[http://en.wikipedia.org/wiki/Instruction_prefetch Instruction prefetch wiki article.]</ref><br />
<br />
=== Types of prefetching ===<br />
<br />
[http://en.wikipedia.org/wiki/Instruction_prefetch Prefetching] can be primarily classified based on whether it is binding or non-binding, and whether it is hardware or software controlled. Using a binding prefetch, the value of a later reference, like a register load, is bound at the time the prefetch completes. However, this comes with added restrictions because the value in the prefetch might not be accurate, there might be invalidations that can be caused by another processor in the time frame between prefetch and reference by the current processor. Coming to the non-binding prefetch, for the data is got into the processor cache, the coherence is maintained till the processor reads or writes the value. This approach unlike binding prefetch will not have an effect on the correctness of any consistency model. It can serve as a serious improvement in terms of performance.<br />
<br />
The prefetch that is interesting to us is the hardware controlled and non-binding prefetch. Prefetching done is software involves significant effort from the programmers side and it may not be scalable as the length of the program increases. Whereas the non-binding prefetch yields significantly more performance when compared to the binding prefetch. The major performance enhancement from prefetching comes by decreasing the memory latency that are caused by all consistency models. <br />
<br />
In the case of a read operation, the read prefetch is issued to get the data in a read-only shared state in the cache. Since we are considering the non-binding prefetch there is a guarantee that the read operation is going to return a correct value when it is allowed to run, irrespective of the actual prefetch completion time. However there is also a catch to this, the value read might not always be correct. Consider a case where there is a write operation performed on the memory location that was just read-prefetched. Thus the value can be read again depending on whether an invalidation or an update based coherence scheme is being used. If an [http://en.wikipedia.org/wiki/Cache_coherence update based coherence scheme] is being used, we can be assured that the other processor sends a bus update and the current processor can pick it up to update its value. However, if an invalidation based coherence scheme is used, there would be a coherence miss and the value will be read again from the system memory giving an illusion that the prefetch did not occur.<br />
<br />
In the case of a write operation, to acquire the exclusive ownership of the line, a read-exclusive prefetch can be used. Since it is cached in the exclusive mode, a write operation can proceed without incurring an invalidate or an update on other caches which have cached the same line or block. The write operation finishes quickly because the value is already cached and there is no coherence miss, thus reducing the idle time of the processor. However, it is to be noted that the read-exclusive prefetch is only possible if the coherence scheme is invalidation based and not an update one. The same logic of incorrectness applies here that we have seen in the read case, suppose that another processor asks for a write to the same block, the exclusive ownership will no longer be maintained. Instead the cache block will be invalidated.<br />
<br />
=== How does prefetching work ? ===<br />
<br />
In a multiprocessor environment, each processor has a [http://en.wikipedia.org/wiki/Memory_disambiguation load] and a [http://en.wikipedia.org/wiki/Memory_disambiguation store buffer]. The way in which consistency models work are that the accesses to memory locations are delayed until the previous requests have finished. While issuing a read or a write request, we can implement the prefetch by making the hardware automatically issue a prefetch for requests which are in the load or store buffer and those requests which cannot be honored right away because of the delays incurred due to consistency model constraints. <br />
<br />
Let us trace through the steps a prefetch request would follow. First it looks up the cache to see whether the block is already present. If it is indeed available, the request is terminated. If it is not present, the prefetch is issued to memory. Depending on the type of prefetch technique we are using, the response to the prefetch might be immediate or not. The response is then placed in the cache. This process can be optimized by detecting duplicate requests to the same location and then combining the responses to each individual request to point to the prefetch request, thereby preventing duplicate requests being issued to memory. This mechanism also taxes the system in the form of requirements. Firstly, it requires hardware coherent caches and the the block that is prefetched should fit into the cache. Then for the write prefetch to work efficiently, there should be an invalidation based coherence scheme in place. Not only these, the bus bandwidth should be high in order to handle several prefetch requests at the same time. The caches will also be more busy with read write transactions when prefetching is implemented.<ref>[http://www.opensparc.net/pubs/papers/InstrPfHPCA05.pdf Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications]</ref> <br />
<br />
The amount of lookahead we do for a prefetch needs to be controlled, in the sense that if more number of blocks are prefetched than required, then the processor might not ever use it and it would also result in increased cache misses of actually required blocks. Thus the extent to which lookahead is done should dynamically adjust depending on whether the processor actually uses the blocks or just evicts them without a read or a write reference to it.<br />
<br />
== Prefetching with Sequential Consistency ==<br />
<br />
Sequential Consistency (SC) might cause a reader to assume that its implementation will need a single memory module. However, this is not true. Both SC and the relaxed memory models allow many optimizations within them in order to deliver high performance. SC and the relaxed models allow non-binding prefetching along with coherent caching.<ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&sqi=2&ved=0CCkQFjAA&url=ftp%3A%2F%2Fftp.cs.wisc.edu%2Fpub%2Ftechreports%2F1991%2FTR1006.pdf&ei=cZ57T-j7DNCbtwenqIG1CA&usg=AFQjCNHtHiuYi2hYaVbTkSuELNg7PNQuXA&sig2=VFMR7Hq3ofiDnH8tzbFNUg Cache consistency and sequential consistency]</ref><br />
<br />
'''Let us take a look at an example and see how SC vs prefetching with SC performs'''<br />
<br />
Assumptions being made are that the processor has non-blocking reads with branch prediction machinery, an invalidation based cache coherence scheme is in place, if there is a cache hit the latency is 1 clock cycle and the cache miss incurs a latency of 100 clock cycles. <br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Since we are considering a system with SC, we know that an access to memory cannot be issued until the previous access has completed. The first three accesses are misses and they occur one after the other without any interleaving, which gives us a total latency of 100 x 3 = 300 clock cycles. The fourth operation however is a cache hit, thus adding only 1 clock cycle. The four accesses take up 301 clock cycles to complete.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance. Since the system has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
Comparing the 103 clock cycles in prefetching under SC .vs. SC only we see that there is nearly a 200 clock cycle difference which is a significant improvement. As the number of accesses increase, the difference is only going to get larger until a certain point where "SC only" would no longer be a viable option.<br />
<br />
'''Another example showing how SC vs prefetching with SC performs'''<br />
<br />
The same assumptions are being made which we made for the first example.<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under SC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under SC only we see that the total number of clock cycles are 302.<br />
<br />
[[Measuring how the same code performs under prefetching with SC]]<br />
<br />
With prefetching, we see that the total time taken will be 203 (2 misses & 3 hits).<br />
<br />
Thus again, we see that prefetching with SC performs better than "SC only".<br />
<br />
== Performance of prefetching with SC and why the idea has not been widely adopted ==<br />
<br />
We have seen two examples, where prefetching with SC does a better job than "SC only". But what we need to look at is whether this is the maximum performance which we can extract. Consider the second example where we had 3 reads in a critical section. The address which E[D] is trying to access will depend on the value of D. Read D was a cache hit, and E[D] is not allowed to perform under SC until the read C finishes. Thus, even though prefetching increases performance by reducing the time delay caused due to consistency constraints, it does not deal with situations where out of order usage of the values returned by memory access is critical for the processor to proceed efficiently. In other words, prefetching fails to do a good job when out of order consumption of values is important.<ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 Memory access dependencies in shared-memory multiprocessors]</ref><ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0CDIQFjAA&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.52.9935%26rep%3Drep1%26type%3Dpdf&ei=wp17T_vaKsrEtwe9yvSpCA&usg=AFQjCNGQXk84yrSUHkZU-mDw0D8KMVb6WQ&sig2=rhKqMuWKvTBHdFgK3rOthw Performance evaluation of memory consistency models for shared-memory multiprocessors]</ref><br />
<br />
Even though the main use of prefetching is to enable servicing of the requests faster when compared to the delay constraints imposed by the memory contraint models, correctness needs to be maintained at all times. The number of times a prefetched value is incorrect should be small, and luckily this is indeed true in real world systems for several reasons. The invalidation of the prefetched values is loosely coupled with the delay to obtain a correct execution sequence. These delays are imposed by the memory consistency models, and in SC which is the stricter of all models, imposes many delays. Usually, the time when one process releases a synchronization is much earlier when compared another process trying to acquire it. Thus the delays introduced by SC are unnecessary and therefore it taxes the systems performance. <ref>[http://dl.acm.org/citation.cfm?id=285991 Memory access buffering in multiprocessors]</ref><br />
<br />
Such cases are not rare to find in real applications and hence prefetching cannot be used all the time. Therefore prefetching under SC was not widely adopted and hence new schemes had to be developed in order to overcome the drawbacks of the current method.<br />
<br />
== Solution#1 Prefetching with Release Consistency ==<br />
<br />
Prefetching under release consistency does at least as good as prefetching under SC. Let us evaluate its performance in the two examples we looked at previously. We follow the same assumptions about the system which we have followed previously.<br />
<br />
'''The first example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) write A (miss)<br />
3) write B (miss)<br />
4) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Since we are considering a system with RC, we know that write accesses to memory are delayed until the lock access can be performed. The lock L operation takes 100 clock cycles to finish, followed by another 100+1 cycles for write A, write B to finish and then finally the fourth operation takes 1 clock cycle to finish because it is a hit. Thus the total number of clock cycles are 202 under the "RC only" approach.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching we can get significant improvement in terms of performance, atleast with SC. Since the system now has the ability to do prefetching and the processor has branch prediction machinery, let us assume that the branch predictor takes the loop in which the lock L has been successfully acquired. The lookahead operates and A and B are prefetched into memory in the read exclusive mode. When the statement lock L executes, the write accesses to A and B are served in parallel as well because they are prefetched. Thus the total would sum to 102 clock cycles (2 hits in parallel and 1 miss). The fourth memory access is a hit and takes only 1 clock cycle to finish thus giving a total of 103 clock cycles.<br />
<br />
In this example, we found that prefetching with SC and prefetching with RC take the amount of time.<br />
<br />
'''The second example'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
[[Measuring how the code performs under RC only]]<br />
<br />
Under the critical section we see that there are three read accesses. Read D is assumed to be a hit and read E[D] may be a hit or a miss depending on the value D. Doing the same math that we have done above, under "RC only" we can see that the total number of clock cycles are 203.<br />
<br />
[[Measuring how the same code performs under prefetching with RC]]<br />
<br />
With prefetching, we see that the total time taken will be 202 (2 misses & 2 hits pipelined).<br />
<br />
Thus again, we see that prefetching with RC performs better than "RC only".<br />
<br />
However, we have not got a significant performance gain in the second example. Thus even though RC allows more relaxation on the order of operations issued to memory, the gain is not much. Relaxed models offer more options on the hardware implementation perspective than SC, so we might get tempted to conclude that hardware must use the relaxed models instead of SC. On the other hand, the performance gain we expect too get is not being delivered under prefetching with RC, thus it cannot be justified to be a good approach either. Even though it performs better than prefetching under SC.<br />
<br />
Also, the same argument that we used for SC by mentioning that it taxes the system by causing unwanted delays to ensure correctness can be applied to the RC model as well. Though unlike SC, it may not tax the systems performance much, because in RC the delays are only inserted at synchronization points. Even then it forms a part of the argument that prefetching under RC is not a very good method.<br />
<br />
== Solution#2 Speculative Execution ==<br />
<br />
Speculative execution does impose many constraints which relaxed and SC implementations do, but rather it allows them to be more aggressive. Speculative execution allows the processor to execute instructions eagerly. However the same strictness when it comes to being correct applies. That is the instructions must be undone when speculations prove incorrect. This scenario can be found in wrongly predicted branches. When the processor knows that it cannot be wrong, it does a commit of the instruction which frees up the resources that were being used for implementation. There are two strict rules about instructions being committed: <ref>[http://en.wikipedia.org/wiki/Speculative_execution Speculative Execution wiki article]</ref><br />
<br />
- All instructions prior to the current instruction must be committed, &<br />
- The current instruction operation commits.<br />
<br />
For example, when we consider a load or store operation, we can be assured that it commits when it does a read or a write on a memory value. With speculative execution, both relaxed and SC implementations can perform operations out of order and in a speculative fashion. While comparing the peer performance of relaxed .vs. SC,<br />
<br />
read A (miss)<br />
read B (hit)<br />
<br />
When dealing with SC, read A occurs first, gets committed and then read B gets committed. However, with relaxed models, read B can get committed before read A gets committed. The difference in performance between relaxed and SC is very narrow. However, the measurement of the difference in performance depends upon benchmarks, latencies etc.<br />
<br />
The figure below shows an example implementation of a SE system.<ref>[http://www.csl.cornell.edu/courses/ee572/gharachorloo.icpp91.pdf Two Techniques to Enhance the Performance of Memory Consistency Models by Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]</ref><br />
<br />
[[File:SE_implementation.png|600px|Example implementation of a SE system. Source: Two Techniques to Enhance the Performance of Memory Consistency Models by<br />
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy]]<br />
<br />
=== Idea behind speculative execution ===<br />
<br />
The core idea which forms the crux of speculative execution is simple and easy to understand. For example, let us consider there are two accesses a and b in the program order. a is considered to have a large latency whereas b is simply a load access. Also, the consistency model needs a to complete before b can finish. The speculative execution for load accesses proceeds as follows. The processor obtains the value returned by access b before a can complete and it proceeds. Now when a completes, the processor checks to see if the speculated return value of b before the completion of a is same as the actual value obtained after a completes. If they both match then the speculation was correct and the processor proceeds without any undo of instructions. However, if the values do not match then we need to redo access b to get the correct value <ref>[http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDUQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.57.1560%26rep%3Drep1%26type%3Dpdf&ei=lbB8T8DZKtKCtgeJ7v3mDA&usg=AFQjCNElr6qsvxH41INvR6tY12S4mDwLeQ&sig2=dk_gxOC4J7VEPz3I5EOgXA Speculative Execution in Real-Time Systems]</ref>. These steps in speculative execution can be summarized by 3 different mechanisms. Namely,<br />
<br />
a) The speculative mechanism<br />
b) The detection mechanism<br />
c) The correction mechanism<br />
<br />
'''a) The speculative mechanism -''' In the speculative mechanism, the most appropriate thing to do would be to perform the access, get the returned value and proceed to use the returned value. If there is a cache hit, the value will be returned instantly, else if it is a miss the access is pipelined with other accesses just like we have seen in prefetching.<br />
<br />
'''b) The detection mechanism -''' The way to detect if the speculated value is correct or not, is by redoing the access after the consistency model would have actually allowed it do be done without speculation. This however might not be the only way. If we could monitor the coherence transactions on that particular location in cache to see if there is an invalidation then the detection process can be faster. Thus another improvement when compared to the prefetch technique is that, in speculative execution the cache is only accessed once unlike twice which is the norm in prefetch technique. Going back to our example of two accesses a and b, the consistency model requires that access b is deferred until access a is complete. However, under the speculative execution, b can proceed without waiting for a to complete. The detection mechanism works by monitoring whether there is an update or invalidation at location b which is an indication that the speculation is incorrect. However, if there are no update or invalidation messages, we can be assured that the speculated value was correct.<br />
<br />
'''c) The correction mechanism -''' Once the detection mechanism determines that the speculated value is incorrect, the correction mechanism comes into play. The first step that the correction mechanism does is that it discards the computation of the speculated value. The load accesses and the computations after the speculated value can be discarded too, just like the correction mechanism used in processors when there is a branch prediction that has gone wrong.<br />
<br />
The figure below, shows the organization of a load/store functional unit of a SE system.<br />
<br />
[[File:Load_store.png|600px|Organization of a load store functional unit]]<br />
<br />
The speculative mechanism is superior to the prefetch mechanism (both under SC and RC) by giving an opportunity to use out of order speculated values.<br />
<br />
'''Referring back to the example we discussed while talking about performance of prefetching with RC/SC'''<br />
<br />
The following code segment represents a common producer scenario:<br />
<br />
1) lock L (miss)<br />
2) read C (miss)<br />
3) read D (hit)<br />
4) read E[D] (miss)<br />
5) unlock L (hit)<br />
<br />
The pipelining in both prefetching and speculative execution will be same and thus we might expect the same level of performance. But however read D does not cause a bottle neck because under speculative execution, its value can be immediately consumed before the previous accesses commit. Thus we expect both the SC and RC implementations to finish in 104 clock cycles (analogous to 4 hits and 1 miss).<br />
<br />
As soon as we know the address for the access, the load access can be issued under speculative execution irrespective of the consistency model that is being supported. Even speculative execution will impose requirements on the system. For all the three mechanisms discussed, we expect hardware support, else we might not get the performance gain that we expect if we implement the same in software.<ref>[http://impact.crhc.illinois.edu/ftp/conference/micro-93-suppression.pdf Speculative Execution Exception Recovery using Write-back Suppression]</ref><br />
<br />
=== Illustrative example ===<br />
<br />
This is the example which we will be taking up for discussion to see how SE works,<br />
<br />
[[File:SE_example.png|600px|Organization of a load store functional unit]]<br />
<br />
In the above figure, the contents of various buffers are showed along with the cache content for each event that occurs. All three mechanisms which we have discussed will be traced in the example. The reorder buffer holds the instructions that are fetched and decoded. Tracing through the set of events, initially the loads and prefetches (exclusive mode) are issued for the corresponding stores. In the meantime, while the store buffer is working on the store operations, the speculative load buffer has three loads. The returned value of read D has already been used by the processor. The second event indicates an ownership for B, however it is not immediately completed. Its completion has been reordered and delayed by the reorder buffer. The third event indicates that the value of A arrives and the entrees for A are purged from both the speculative-load and reorder buffers. Once the load A completes the reorder buffer signals the store buffer to allow the store B to complete. And this is a hit because the value is already cached and thus finishes quickly. Store C is next to be served in the reorder buffer and its access is merged with the previous prefetch request for the same location.<ref>[http://www.cs.waikato.ac.nz/timewarp/wengine/papers/gc99_1/ Data and Control Speculative Execution]</ref><br />
<br />
Now to make things interesting, let us assume that there is an invalidation for D. This would cause a mismatch in the value speculated for D and hence the load D and the instructions following it are purged, indicated by event 5. The 6th event shows the correction mechanism by fetching the two instructions again and yet again load D will be a speculative event because store C has not finished. The 7th event shows new value in location D and since it is cached and its value known, E[D] proceeds. The 8th event shows that store C has finished and since it does not effect D, the speculative value is correct and and is retired from the reorder and speculative-load buffers. The last even signifies the completion of E[D].<br />
<br />
== Future directions and ambitious implementations ==<br />
<br />
The paper by Adve and Hill <ref>[ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.pdf Implementing Sequential Consistency In Cache-Based Systems]</ref> proposes an implementation for sequential consistency that is more efficient than conventional implementations. Their scheme requires an invalidation-based cache coherence protocol. At points where a conventional implementation stalls for the full latency of pending writes, their implementation stalls only until ownership is gained. To make the implementation satisfy sequential consistency, the new value written is not made visible to other processors until all previous writes by this processor have completed. The gains from this are expected to be limited, however, since the latency of obtaining ownership is often only slightly smaller than the latency for the write to complete. In addition, the proposed scheme has no provision for hiding the latency of read accesses. Since the visibility-control mechanism reduces the stall time for writes only slightly and does not affect the stall time for reads, its performance wont be much better than conventional implementations. In contrast, the prefetch and speculative load techniques provide much greater opportunity for buffering and pipelining of read and write accesses.<br />
<br />
The paper by Stenstrom <ref>[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=223075&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D223075 A latency-hiding scheme for multiprocessors with buffered multistage networks]</ref> proposes a mechanism for guaranteeing access order at the memory instead of at the processor. Each request contains a processor identification and a sequence number. Consecutive requests from the same processor get consecutive sequence numbers. Each memory module has access to a common data structure called next sequence-number table (NST). The NST contains P entries, one entry per processor. Each entry contains the sequence number of the next request to be performed by the corresponding processor. This allows the mechanism to guarantee that accesses from each processor are kept in program order. Theoretically, this scheme can enhance the performance of sequential consistency. However, the major disadvantage is that caches are not allowed. This can severely hinder the performance when compared to implementations that allow shared locations to be cached.<br />
<br />
To gain significant improvement in terms of performance, there have been a number of memory consistency models proposed. One disadvantage of the relaxed memory consistency models is that they present a more complex programming model to the user. The cost of this added performance benefit is however the extra hardware complexity that comes with it. The prefetch technique is simple and can easily be absorbed into the modern multi processor architectures while the speculative execution technique is not that easy when compared to the prefetch technique. Things get more complicated when the speculative execution technique is to be incorporated into multi processor systems when compared to uni processor systems. In future, we might expect better implementations of the speculative execution technique which will make this transition easy.<br />
<br />
== References ==<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=58242CSC/ECE 506 Spring 2012/1a mw2012-02-07T04:32:29Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<p>Since supercomputers have existed, as technology has advanced, they have continued to be surpassed by one another. This has lead to a drive for engineers and scientists to design and create supercomputers that continue to outperform others<ref>http://en.wikipedia.org/wiki/Supercomputer#History</ref>. This article compares current supercomputers as well as supercomputer architectures.</p><br />
<p>For the history, development and current state of supercomputing, including a fairly recent, detailed top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry a fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|thumb|right|upright|300px|Current distribution of architecture types among the top 500 supercomputers. Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|thumb|right|upright|325px|Number of cluster systems among the top 500 supercomputers since before 2000. Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|thumb|right|upright|325px|Number of MPP systems among the top 500 supercomputers since before 1995. Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|thumb|right|upright|350px|Number of constellation systems among the top 500 supercomputers since before 2000. Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|thumb|right|upright|350px|Daily computing power (TFLOPS) of grid supercomputers over a several month period. Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [http://www.GridRepublic.org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Top 10 Supercomputers =<br />
<p>According to [http://www.top500.org/ Top500.org], the top 10 supercomputers in the world, as of November 2011, are listed below:</p><br />
{|class="wikitable"<br />
!Number<br />
!Name<br />
!System<br />
|-<br />
|1<br />
|K computer<br />
|[http://www.top500.org/system/177232 SPARC64 VIIIfx 2.0GHz, Tofu interconnect]<br />
|-<br />
|2<br />
|Tianhe-1A<br />
|[http://www.top500.org/system/176929 NUDT YH MPP, Xeon X5670 6C 2.93 GHz, NVIDIA 2050]<br />
|-<br />
|3<br />
|Jaguar<br />
|[http://www.top500.org/system/176544 Cray XT5-HE Opteron 6-core 2.6 GHz]<br />
|-<br />
|4<br />
|Nebulae<br />
|[http://www.top500.org/system/176819 Dawning TC3600 Blade, Intel X5650, NVidia Tesla C2050 GPU]<br />
|-<br />
|5<br />
|TSUBAME 2.0<br />
|[http://www.top500.org/system/176927 HP ProLiant SL390s G7 Xeon 6C X5670, Nvidia GPU, Linux/Windows]<br />
|-<br />
|6<br />
|Cielo<br />
|[http://www.top500.org/system/177170 Cray XE6, Opteron 6136 8C 2.40GHz, Custom]<br />
|-<br />
|7<br />
|Pleiades<br />
|[http://www.top500.org/system/177259 SGI Altix ICE 8200EX/8400EX, Xeon HT QC 3.0/Xeon 5570/5670 2.93 Ghz, Infiniband]<br />
|-<br />
|8<br />
|Hopper<br />
|[http://www.top500.org/system/176952 Cray XE6, Opteron 6172 12C 2.10GHz, Custom]<br />
|-<br />
|9<br />
|Tera-100<br />
|[http://www.top500.org/system/176928 Bull bullx super-node S6010/S6030]<br />
|-<br />
|10<br />
|Roadrunner<br />
|[http://www.top500.org/system/176027 BladeCenter QS22/LS21 Cluster, PowerXCell 8i 3.2 Ghz / Opteron DC 1.8 GHz, Voltaire Infiniband]<br />
|}<br />
<p>For a more detailed version of this list, see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry#Top_10_supercomputers_of_today.5B9.5D a fellow student's wiki on supercomputers].</p><br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|}<br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=58219CSC/ECE 506 Spring 2012/1a mw2012-02-07T03:47:06Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
<p>For the history, development and current state of supercomputing, including a fairly recent, detailed top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry a fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|thumb|right|upright|300px|Current distribution of architecture types among the top 500 supercomputers. Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|thumb|right|upright|325px|Number of cluster systems among the top 500 supercomputers since before 2000. Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|thumb|right|upright|325px|Number of MPP systems among the top 500 supercomputers since before 1995. Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|thumb|right|upright|350px|Number of constellation systems among the top 500 supercomputers since before 2000. Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|thumb|right|upright|350px|Daily computing power (TFLOPS) over a several month period. Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [http://www.GridRepublic.org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Top 10 Supercomputers =<br />
<p>According to [http://www.top500.org/ Top500.org], the top 10 supercomputers in the world, as of November 2011, are listed below:</p><br />
{|class="wikitable"<br />
!Number<br />
!Name<br />
!System<br />
|-<br />
|1<br />
|K computer<br />
|[http://www.top500.org/system/177232 SPARC64 VIIIfx 2.0GHz, Tofu interconnect]<br />
|-<br />
|2<br />
|Tianhe-1A<br />
|[http://www.top500.org/system/176929 NUDT YH MPP, Xeon X5670 6C 2.93 GHz, NVIDIA 2050]<br />
|-<br />
|3<br />
|Jaguar<br />
|[http://www.top500.org/system/176544 Cray XT5-HE Opteron 6-core 2.6 GHz]<br />
|-<br />
|4<br />
|Nebulae<br />
|[http://www.top500.org/system/176819 Dawning TC3600 Blade, Intel X5650, NVidia Tesla C2050 GPU]<br />
|-<br />
|5<br />
|TSUBAME 2.0<br />
|[http://www.top500.org/system/176927 HP ProLiant SL390s G7 Xeon 6C X5670, Nvidia GPU, Linux/Windows]<br />
|-<br />
|6<br />
|Cielo<br />
|[http://www.top500.org/system/177170 Cray XE6, Opteron 6136 8C 2.40GHz, Custom]<br />
|-<br />
|7<br />
|Pleiades<br />
|[http://www.top500.org/system/177259 SGI Altix ICE 8200EX/8400EX, Xeon HT QC 3.0/Xeon 5570/5670 2.93 Ghz, Infiniband]<br />
|-<br />
|8<br />
|Hopper<br />
|[http://www.top500.org/system/176952 Cray XE6, Opteron 6172 12C 2.10GHz, Custom]<br />
|-<br />
|9<br />
|Tera-100<br />
|[http://www.top500.org/system/176928 Bull bullx super-node S6010/S6030]<br />
|-<br />
|10<br />
|Roadrunner<br />
|[http://www.top500.org/system/176027 BladeCenter QS22/LS21 Cluster, PowerXCell 8i 3.2 Ghz / Opteron DC 1.8 GHz, Voltaire Infiniband]<br />
|}<br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|}<br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=58131CSC/ECE 506 Spring 2012/1a mw2012-02-07T01:49:00Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
<p>For the history, development and current state of supercomputing, including a top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry our fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|right|350px|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [http://www.GridRepublic.org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Top 10 Supercomputers =<br />
<p>According to [http://www.top500.org/ Top500.org], the top 10 supercomputers in the world, as of November 2011, are listed below:</p><br />
{|class="wikitable"<br />
!Number<br />
!Name<br />
!System<br />
|-<br />
|1<br />
|K computer<br />
|[http://www.top500.org/system/177232 SPARC64 VIIIfx 2.0GHz, Tofu interconnect]<br />
|-<br />
|2<br />
|Tianhe-1A<br />
|[http://www.top500.org/system/176929 NUDT YH MPP, Xeon X5670 6C 2.93 GHz, NVIDIA 2050]<br />
|-<br />
|3<br />
|Jaguar<br />
|[http://www.top500.org/system/176544 Cray XT5-HE Opteron 6-core 2.6 GHz]<br />
|-<br />
|4<br />
|Nebulae<br />
|[http://www.top500.org/system/176819 Dawning TC3600 Blade, Intel X5650, NVidia Tesla C2050 GPU]<br />
|-<br />
|5<br />
|TSUBAME 2.0<br />
|[http://www.top500.org/system/176927 HP ProLiant SL390s G7 Xeon 6C X5670, Nvidia GPU, Linux/Windows]<br />
|-<br />
|6<br />
|Cielo<br />
|[http://www.top500.org/system/177170 Cray XE6, Opteron 6136 8C 2.40GHz, Custom]<br />
|-<br />
|7<br />
|Pleiades<br />
|[http://www.top500.org/system/177259 SGI Altix ICE 8200EX/8400EX, Xeon HT QC 3.0/Xeon 5570/5670 2.93 Ghz, Infiniband]<br />
|-<br />
|8<br />
|Hopper<br />
|[http://www.top500.org/system/176952 Cray XE6, Opteron 6172 12C 2.10GHz, Custom]<br />
|-<br />
|9<br />
|Tera-100<br />
|[http://www.top500.org/system/176928 Bull bullx super-node S6010/S6030]<br />
|-<br />
|10<br />
|Roadrunner<br />
|[http://www.top500.org/system/176027 BladeCenter QS22/LS21 Cluster, PowerXCell 8i 3.2 Ghz / Opteron DC 1.8 GHz, Voltaire Infiniband]<br />
|}<br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|}<br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=58121CSC/ECE 506 Spring 2012/1a mw2012-02-06T22:50:58Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
<p>For the history, development and current state of supercomputing, including a top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry our fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|right|350px|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Top 10 Supercomputers =<br />
<p>According to [http://www.top500.org/ Top500.org], the top 10 supercomputers in the world, as of November 2011, are listed below:</p><br />
{|class="wikitable"<br />
!Number<br />
!System<br />
|-<br />
|1<br />
|[http://www.top500.org/system/177232 SPARC64 VIIIfx 2.0GHz, Tofu interconnect]<br />
|-<br />
|2<br />
|[http://www.top500.org/system/176929 NUDT YH MPP, Xeon X5670 6C 2.93 GHz, NVIDIA 2050]<br />
|-<br />
|3<br />
|[http://www.top500.org/system/176544 Cray XT5-HE Opteron 6-core 2.6 GHz]<br />
|-<br />
|4<br />
|[http://www.top500.org/system/176819 Dawning TC3600 Blade, Intel X5650, NVidia Tesla C2050 GPU]<br />
|-<br />
|5<br />
|[http://www.top500.org/system/176927 HP ProLiant SL390s G7 Xeon 6C X5670, Nvidia GPU, Linux/Windows]<br />
|-<br />
|6<br />
|[http://www.top500.org/system/177170 Cray XE6, Opteron 6136 8C 2.40GHz, Custom]<br />
|-<br />
|7<br />
|[http://www.top500.org/system/177259 SGI Altix ICE 8200EX/8400EX, Xeon HT QC 3.0/Xeon 5570/5670 2.93 Ghz, Infiniband]<br />
|-<br />
|8<br />
|[http://www.top500.org/system/176952 Cray XE6, Opteron 6172 12C 2.10GHz, Custom]<br />
|-<br />
|9<br />
|[http://www.top500.org/system/176928 Bull bullx super-node S6010/S6030]<br />
|-<br />
|10<br />
|[http://www.top500.org/system/176027 BladeCenter QS22/LS21 Cluster, PowerXCell 8i 3.2 Ghz / Opteron DC 1.8 GHz, Voltaire Infiniband]<br />
|}<br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
<table border = 1><br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|-<br />
</table><br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=58113CSC/ECE 506 Spring 2012/1a mw2012-02-06T22:31:34Z<p>Mbplautz: /* Top 10 Supercomputers */</p>
<hr />
<div>$wgLogo = "http://152.1.226.18/graphics_v3/level2/campus_resources2.jpg";<br />
<br />
<p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
<p>For the history, development and current state of supercomputing, including a top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry our fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|right|350px|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Top 10 Supercomputers =<br />
<p>According to [http://www.top500.org/ Top500.org], the top 10 supercomputers in the world, as of November 2011, are listed below:</p><br />
{|class="wikitable"<br />
!Number<br />
!System<br />
|-<br />
|1<br />
|[http://www.top500.org/system/177232 SPARC64 VIIIfx 2.0GHz, Tofu interconnect]<br />
|-<br />
|2<br />
|[http://www.top500.org/system/176929 NUDT YH MPP, Xeon X5670 6C 2.93 GHz, NVIDIA 2050]<br />
|-<br />
|3<br />
|[http://www.top500.org/system/176544 Cray XT5-HE Opteron 6-core 2.6 GHz]<br />
|-<br />
|4<br />
|[http://www.top500.org/system/176819 Dawning TC3600 Blade, Intel X5650, NVidia Tesla C2050 GPU]<br />
|-<br />
|5<br />
|[http://www.top500.org/system/176927 HP ProLiant SL390s G7 Xeon 6C X5670, Nvidia GPU, Linux/Windows]<br />
|-<br />
|6<br />
|[http://www.top500.org/system/177170 Cray XE6, Opteron 6136 8C 2.40GHz, Custom]<br />
|-<br />
|7<br />
|[http://www.top500.org/system/177259 SGI Altix ICE 8200EX/8400EX, Xeon HT QC 3.0/Xeon 5570/5670 2.93 Ghz, Infiniband]<br />
|-<br />
|8<br />
|[http://www.top500.org/system/176952 Cray XE6, Opteron 6172 12C 2.10GHz, Custom]<br />
|-<br />
|9<br />
|[http://www.top500.org/system/176928 Bull bullx super-node S6010/S6030]<br />
|-<br />
|10<br />
|[http://www.top500.org/system/176027 BladeCenter QS22/LS21 Cluster, PowerXCell 8i 3.2 Ghz / Opteron DC 1.8 GHz, Voltaire Infiniband]<br />
|}<br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
<table border = 1><br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|-<br />
</table><br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=58112CSC/ECE 506 Spring 2012/1a mw2012-02-06T22:28:10Z<p>Mbplautz: </p>
<hr />
<div>$wgLogo = "http://152.1.226.18/graphics_v3/level2/campus_resources2.jpg";<br />
<br />
<p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
<p>For the history, development and current state of supercomputing, including a top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry our fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|right|350px|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Top 10 Supercomputers =<br />
<p>According to [http://www.top500.org/ Top500.org], the top 10 supercomputers in the world, as of February 2012, are listed below:</p><br />
{|class="wikitable"<br />
!Number<br />
!System<br />
|-<br />
|1<br />
|SPARC64 VIIIfx 2.0GHz, Tofu interconnect <br />
|-<br />
|2<br />
|NUDT YH MPP, Xeon X5670 6C 2.93 GHz, NVIDIA 2050<br />
|-<br />
|3<br />
|Cray XT5-HE Opteron 6-core 2.6 GHz<br />
|-<br />
|4<br />
|Dawning TC3600 Blade, Intel X5650, NVidia Tesla C2050 GPU<br />
|-<br />
|5<br />
|HP ProLiant SL390s G7 Xeon 6C X5670, Nvidia GPU, Linux/Windows<br />
|-<br />
|6<br />
|Cray XE6, Opteron 6136 8C 2.40GHz, Custom<br />
|-<br />
|7<br />
|SGI Altix ICE 8200EX/8400EX, Xeon HT QC 3.0/Xeon 5570/5670 2.93 Ghz, Infiniband<br />
|-<br />
|8<br />
|Cray XE6, Opteron 6172 12C 2.10GHz, Custom<br />
|-<br />
|9<br />
|Bull bullx super-node S6010/S6030<br />
|-<br />
|10<br />
|BladeCenter QS22/LS21 Cluster, PowerXCell 8i 3.2 Ghz / Opteron DC 1.8 GHz, Voltaire Infiniband<br />
|}<br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
<table border = 1><br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|-<br />
</table><br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57996CSC/ECE 506 Spring 2012/1a mw2012-02-05T21:11:14Z<p>Mbplautz: </p>
<hr />
<div>$wgLogo = "http://152.1.226.18/graphics_v3/level2/campus_resources2.jpg";<br />
<br />
<p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
<p>For the history, development and current state of supercomputing, including a top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry our fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|right|350px|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
<table border = 1><br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|-<br />
</table><br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57995CSC/ECE 506 Spring 2012/1a mw2012-02-05T21:10:22Z<p>Mbplautz: </p>
<hr />
<div>$wgLogo = "http://152.1.226.18/graphics_v3/level2/campus_resources2.jpg"<br />
<br />
<p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
<p>For the history, development and current state of supercomputing, including a top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry our fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|right|350px|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
<table border = 1><br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|-<br />
</table><br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57994CSC/ECE 506 Spring 2012/1a mw2012-02-05T21:04:14Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
<p>For the history, development and current state of supercomputing, including a top 10 list, please see [http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_ry our fellow student's wiki article on Supercomputers].</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
[[File:2011nov-top500-architecture.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture. The Massively Parallel Processing section of the graph makes up 17.8% of the total number of current supercomputers. The bulk of supercomputers is made up of clustered systems, which Constellation architectures make up a fraction of a percent of supercomputers. Each architecture is further discussed, below.</p><br />
<br />
== Cluster ==<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The chart to the right shows the growth of cluster supercomputer systems with the oldest data on the right. Teh number of clustered supercomputer systems grew rapidly during the 21st century and started leveling off after about 7.5 years.</p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
[[File:2011nov-top500-mpp-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown on the right. MPP supercomputer systems grew from the early 90's until the early part of the 21st century and have since declined in total number.</p><br />
<br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
[[File:2011nov-top500-constellation-count.png|right|350px|Image from i.TOP500.org/stats]]<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011. The graph shows rapid growth and decline in the first 5 years of the 21st century.</p><br />
<br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
[[File:20120130-grid-computing-graph.png|right|350px|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world.</p><br />
<br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats</ref>.</p><br />
<br />
= Advantages & Disadvantages of Supercomputers =<br />
<br />
<p>An excellent way to compare the advantages and disadvantages of supercomputers is to use a table. Although this list is not exhaustive, it generally sums up the advantages as being the ability solve large number crunching problems quickly but at a high cost due to the specialty of the hardware, the physical scale of the system and power requirements.</p><br />
<br />
<table border = 1><br />
{|class="wikitable"<br />
!Advantage<br />
!Disadvantage<br />
|-<br />
|Ability to process large amounts of data. Examples include atmospheric modeling and oceanic modeling. Processing large matrices and weapons simulation<ref name="paulmurphy">http://www.zdnet.com/blog/murphy/uses-for-supercomputers/746 Murphy, Paul (December 2006) Uses for supercomputers</ref>.<br />
|Limited scope of applications, or in general, they're not general purpose computers. Supercomputers are usually engaged in scientific, military or mathematical applications<ref name="paulmurphy" />.<br />
|-<br />
|The ability to process large amounts of data quickly and in parallel, when compared to the ability of low end commercial systems or user computers<ref>http://nickeger.blogspot.com/2011/11/supercomputers-advantages-and.html Eger, Nick (November 2011) Supercomputer advantages adn disadvantages</ref>.<br />
|Cost, power and cooling. Commercial supercomputers costs hundreds of millions of dollars. They have on-going energy and cooling requirements that are expensive<ref name="robertharris">http://www.zdnet.com/blog/storage/build-an-8-ps3-supercomputer/220?tag=rbxccnbzd1 Harris, Robert (October 2007) Build an 8 PS3 supercomputer</ref>.<br />
|-<br />
</table><br />
<br />
<p>Although these are advantages and disadvantages of the traditional supercomputer, there is movement towards the consumerization of supercomputers which could result in supercomputers being affordable to the average person<ref name="robertharris" />.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<br />
Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The statistics tracked by [http://www.GridRepublic.org GridRepublic.org] for 55 applications shows that grid computing is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN located at the Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, and Tofu interconnect that operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57590CSC/ECE 506 Spring 2012/1a mw2012-01-31T03:58:34Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The following graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture:</p><br />
<br />
[[File:2011nov-top500-architecture.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
== Cluster ==<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The following chart shows the growth of cluster supercomputer systems with the oldest data on the right:</p><br />
<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown below:</p><br />
<br />
[[File:2011nov-top500-mpp-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011:</p><br />
<br />
[[File:2011nov-top500-constellation-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The following graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world:</p><br />
<br />
[[File:20120130-grid-computing-graph.png|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Image from GridRepublic.org<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats Image from GridRepublic.Org</ref></p><br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats" /></p>.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<p>Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The [http://www.GridRepublic.org GridRepublic.org] statistics that it tracks for 55 applications is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnectthat operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<p>Your references go here. You should allow the WIKI to create your references list automatically by using inline citations.</p><br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57589CSC/ECE 506 Spring 2012/1a mw2012-01-31T03:58:18Z<p>Mbplautz: </p>
<hr />
<div>$wgLogo="http://152.1.226.18/graphics_v3/level2/campus_resources2.jpg"<br />
<p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The following graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture:</p><br />
<br />
[[File:2011nov-top500-architecture.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
== Cluster ==<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The following chart shows the growth of cluster supercomputer systems with the oldest data on the right:</p><br />
<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown below:</p><br />
<br />
[[File:2011nov-top500-mpp-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011:</p><br />
<br />
[[File:2011nov-top500-constellation-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The following graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world:</p><br />
<br />
[[File:20120130-grid-computing-graph.png|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Image from GridRepublic.org<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats Image from GridRepublic.Org</ref></p><br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats" /></p>.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<p>Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The [http://www.GridRepublic.org GridRepublic.org] statistics that it tracks for 55 applications is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnectthat operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<p>Your references go here. You should allow the WIKI to create your references list automatically by using inline citations.</p><br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57585CSC/ECE 506 Spring 2012/1a mw2012-01-31T03:48:49Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architectures. These architectures are Cluster, Massively Parallel Processing or MPP, and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The following graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture:</p><br />
<br />
[[File:2011nov-top500-architecture.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
== Cluster ==<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The following chart shows the growth of cluster supercomputer systems with the oldest data on the right:</p><br />
<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown below:</p><br />
<br />
[[File:2011nov-top500-mpp-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011:</p><br />
<br />
[[File:2011nov-top500-constellation-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The following graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world:</p><br />
<br />
[[File:20120130-grid-computing-graph.png|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Image from GridRepublic.org<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats Image from GridRepublic.Org</ref></p><br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats" /></p>.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<p>Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The [http://www.GridRepublic.org GridRepublic.org] statistics that it tracks for 55 applications is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnectthat operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<p>Your references go here. You should allow the WIKI to create your references list automatically by using inline citations.</p><br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57583CSC/ECE 506 Spring 2012/1a mw2012-01-31T03:42:36Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to massively outperform typical home and office computers is made possible normally either by an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software is not only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architecture. These architectures are Cluster, Massively Parallel Processing or MPP and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The following graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture:</p><br />
<br />
[[File:2011nov-top500-architecture.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
== Cluster ==<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The following chart shows the growth of cluster supercomputer systems with the oldest data on the right:</p><br />
<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown below:</p><br />
<br />
[[File:2011nov-top500-mpp-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011:</p><br />
<br />
[[File:2011nov-top500-constellation-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The following graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world:</p><br />
<br />
[[File:20120130-grid-computing-graph.png|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Image from GridRepublic.org<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats Image from GridRepublic.Org</ref></p><br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats" /></p>.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<p>Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The [http://www.GridRepublic.org GridRepublic.org] statistics that it tracks for 55 applications is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnectthat operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<p>Your references go here. You should allow the WIKI to create your references list automatically by using inline citations.</p><br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57581CSC/ECE 506 Spring 2012/1a mw2012-01-31T03:38:58Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to outperform typical home and office computers is usually because of an abundance of processor cores or smaller computers working in conjunction together. Supercomputers are generally specialized computers that tend to be very expensive, not available for general-purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software isn't only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architecture. These architectures are Cluster, Massively Parallel Processing or MPP and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The following graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture:</p><br />
<br />
[[File:2011nov-top500-architecture.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
== Cluster ==<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The following chart shows the growth of cluster supercomputer systems with the oldest data on the right:</p><br />
<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown below:</p><br />
<br />
[[File:2011nov-top500-mpp-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011:</p><br />
<br />
[[File:2011nov-top500-constellation-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The following graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world:</p><br />
<br />
[[File:20120130-grid-computing-graph.png|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Image from GridRepublic.org<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats Image from GridRepublic.Org</ref></p><br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats" /></p>.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<p>Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The [http://www.GridRepublic.org GridRepublic.org] statistics that it tracks for 55 applications is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnectthat operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<p>Your references go here. You should allow the WIKI to create your references list automatically by using inline citations.</p><br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57579CSC/ECE 506 Spring 2012/1a mw2012-01-31T03:36:26Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, able to solve complex tasks in a relatively small amount of time. Their ability to outperform typical home and office computers is usually because of an abundance of processor cores or smaller computers working together in conjunction. Supercomputers are generally specialized computers that tend to be very expensive, not available for general purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software isn't only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architecture. These architectures are Cluster, Massively Parallel Processing or MPP and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The following graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture:</p><br />
<br />
[[File:2011nov-top500-architecture.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
== Cluster ==<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The following chart shows the growth of cluster supercomputer systems with the oldest data on the right:</p><br />
<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown below:</p><br />
<br />
[[File:2011nov-top500-mpp-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011:</p><br />
<br />
[[File:2011nov-top500-constellation-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The following graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world:</p><br />
<br />
[[File:20120130-grid-computing-graph.png|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Image from GridRepublic.org<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats Image from GridRepublic.Org</ref></p><br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats" /></p>.<br />
<br />
= Summary of the Comparison of Supercomputers =<br />
<p>Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The [http://www.GridRepublic.org GridRepublic.org] statistics that it tracks for 55 applications is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnectthat operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<p>Your references go here. You should allow the WIKI to create your references list automatically by using inline citations.</p><br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57573CSC/ECE 506 Spring 2012/1a mw2012-01-31T03:29:10Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
<p>[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, usually because of an abundance of processor cores or smaller computers working together in conjunction to solve complex tasks in a relatively small amount of time. Supercomputers are generally specialized computers that tend to be very expensive, not available for general purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software isn't only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
<br />
= Comparison of Supercomputers by Architecture =<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architecture. These architectures are Cluster, Massively Parallel Processing or MPP and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
<br />
<p>The following graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture:</p><br />
<br />
[[File:2011nov-top500-architecture.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
== Cluster ==<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
<br />
<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The following chart shows the growth of cluster supercomputer systems with the oldest data on the right:</p><br />
<br />
[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
<br />
== Massively Parallel Processing, MPP ==<br />
<br />
<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
<br />
<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown below:</p><br />
<br />
[[File:2011nov-top500-mpp-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
<br />
== Constellation ==<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011:</p><br />
<br />
[[File:2011nov-top500-constellation-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
<br />
<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
<br />
<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
<br />
== Grid Computing ==<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
<br />
<p>The following graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world:</p><br />
<br />
[[File:20120130-grid-computing-graph.png|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Image from GridRepublic.org<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats Image from GridRepublic.Org</ref></p><br />
<br />
<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats" /></p>.<br />
<br />
= Conclusion/Summary =<br />
<p>Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The [http://www.GridRepublic.org GridRepublic.org] statistics that it tracks for 55 applications is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnectthat operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
<br />
<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
<br />
= References =<br />
<p>Your references go here. You should allow the WIKI to create your references list automatically by using inline citations.</p><br />
<br />
<references /></div>Mbplautzhttps://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Spring_2012/1a_mw&diff=57571CSC/ECE 506 Spring 2012/1a mw2012-01-31T03:28:21Z<p>Mbplautz: </p>
<hr />
<div><p><b>Comparisons Between Supercomputers</b></p><br />
[http://dictionary.reference.com/browse/supercomputer Supercomputers] are extremely capable computers, usually because of an abundance of processor cores or smaller computers working together in conjunction to solve complex tasks in a relatively small amount of time. Supercomputers are generally specialized computers that tend to be very expensive, not available for general purpose use and are used in computations where large amounts of numerical processing is required. They are used in scientific, military, graphics applications and for other number or data intensive computations <ref>http://dictionary.reference.com/browse/supercomputer Definition of supercomputer</ref>, <ref>http://www.webopedia.com/TERM/S/supercomputer.html Definition of supercomputer</ref>.</p><br />
<br />
= Benchmarking Supercomputers =<br />
<p>Supercomputers are generally compared qualitatively using floating point operations per second, or [http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html FLOPS]. Using standard prefixes, higher levels of FLOPS can be specified as the computing power of supercomputers increases. For example, KiloFLOPS for thousands of FLOPS and MegaFLOPS for millions of FLOPS <ref>http://kevindoran.blogspot.com/2011/04/comparing-performance-of-supercomputers.html Doran, Kevin (April 2011) Comparing the performance of supercomputers</ref>. Often you'll see just the first letter of the prefix with FLOPS. For example, for GigaFLOPS or billions of FLOPS, you'll see [http://top500.org/faq/what_gflop_s GFLOPS] <ref>http://top500.org/faq/what_gflop_s Definition of GFLOPS</ref>.</p><br />
<br />
<p>A software package called [http://www.top500.org/project/linpack LINPACK] is a standard approach to testing or benchmarking supercomputers by solving a dense system of linear equations using the Gauss method. <ref>http://www.top500.org/project/linpack LINPACK defined</ref>. However, LINPACK benchmarking software isn't only used to benchmark supercomputers, it can also be used to benchmark a typical user computer <ref>http://www.xtremesystems.org/forums/showthread.php?197835-IntelBurnTest-The-new-stress-testing-program Intel Benchmark Software</ref>.</p><br />
<br />
= Finding Supercomputer Comparison Data =<br />
<p>Starting in 1993, [http://www.TOP500.org TOP500.org] began collecting performance data on computers and update their list every six months <ref>http://top500.org/faq/what_top500 What is the TOP500</ref>. This appears to be an excellent online source of information that collects benchmark data submitted by users of computers and readily provides performance statistics by Vendor, Application, Architecture and nine (9) other areas <ref name="t500stats">http://i.top500.org/stats TOP500 Stats</ref>. This article, in order to be vendor neutral, is providing the comparison by architecture. However, there are many ways to compare supercomputers and the user interface at [http://www.TOP500.org TOP500.org] makes these comparisons easy to do.</p><br />
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= Comparison of Supercomputers by Architecture =<br />
<p>Traditional supercomputers of today are composed of three (3) types of parallel processing architecture. These architectures are Cluster, Massively Parallel Processing or MPP and Constellation <ref name="t500stats" />. A non-traditional, or disruptive approach, to supercomputers is [http://searchdatacenter.techtarget.com/definition/grid-computing Grid Computing]<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>.</p><br />
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<p>The following graphic generated at [http://www.TOP500.org/ TOP500.org] shows the distribution of supercomputers by architecture:</p><br />
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[[File:2011nov-top500-architecture.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
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== Cluster ==<br />
<p>A [http://searchdatacenter.techtarget.com/definition/cluster-computing Cluster] is a group of computers connected together that appear as a single system to the outside world and provide load balancing and resource sharing <ref>http://searchdatacenter.techtarget.com/definition/cluster-computing Definition of Cluster Computing</ref>. Invented by Digital Equipment Corporation in the 1980's, clusters of computers form the largest number of supercomputers available today <ref>http://books.google.com/books?id=Hd_JlxD7x3oC&pg=PA90&lpg=PA90&dq=what+is+a+constellation+in+parallel+computing?&source=bl&ots=Rf9nxSqOgL&sig=-xleas5wXvNpvkgYYxguvP1tSLA&hl=en&sa=X&ei=aDcnT-XRNqHX0QHymbjrAg&ved=0CGMQ6AEwBw#v=onepage&q=what%20is%20a%20constellation%20in%20parallel%20computing%3F&f=false Applied Parallel Computing</ref>, <ref name="t500stats" />.</p><br />
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<p>[http://www.TOP500.org TOP500.org] data as of November 2011 shows that Cluster computing makes up the largest subset of supercomputers at eight-two percent (82%). The following chart shows the growth of cluster supercomputer systems with the oldest data on the right:</p><br />
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[[File:2011nov-top500-cluster-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
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<p>The total processing power of the top 500 cluster supercomputers is reported at 50,192.82 TFLOPS and the trend for growth of cluster based supercomputers has leveled off<ref name="t500stats" />.</p><br />
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== Massively Parallel Processing, MPP ==<br />
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<p>[http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html Massively Parallel Processing] or MPP supercomputers are made up of hundreds of computing nodes and process data in a coordinated fashion <ref name="ttmppdef">http://whatis.techtarget.com/definition/0,,sid9_gci214085,00.html</ref>. Each node of the MPP generally has its own memory and operating system and can be made up of nodes that have multiple processors and/or multiple cores <ref name="ttmppdef" />.</p><br />
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<p>[http://i.TOP500.org/stats TOP500.org/stats] for the MPP architecture of supercomputers shows that as of November 2011, MPP makes up approximately 17.8% of all supercomputers reported. A graph of the growth and subsequent decline of the MPP architecture from data displayed at [http://i.TOP500.org/stats TOP500.org/stats] is shown below:</p><br />
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[[File:2011nov-top500-mpp-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
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<p>The total processing power of the top 500 MPP supercomputers is 23,823.97 TFLOPS. The trend of MPP supercomputers, like cluster based supercomputers, has leveled off<ref name="t500stats" />.</p><br />
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== Constellation ==<br />
<p>A [http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf Constellation] is a cluster of supercomputers <ref>http://www.mimuw.edu.pl/~mbiskup/presentations/Parallel%20Computing.pdf</ref>. [http://www.TOP500.org TOP500.org] shows only one constellation supercomputer as of November 2011:</p><br />
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[[File:2011nov-top500-constellation-count.png|Image from i.TOP500.org/stats]]<br />
<p><ref name="t500stats" /></p><br />
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<p>This author's speculation about the decline of constellations is based on several factors: Multiple processor and/or multiple core computers have been getting faster and less expensive. Combine these less expensive computers into very large clusters and you can get computing power that rivals a constellation. Alternatively, more and more computers have symmetric multiprocessing, SMP, and the concept of constellations and clusters is converging.</p><br />
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<p>The total processing power of the constellation supercomputer is: 52.84 TFLOPS<ref name="t500stats" />.</p><br />
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== Grid Computing ==<br />
<p>Grid Computing is defined as applying many networked computers to solving a single problem simultaneously<ref>http://searchdatacenter.techtarget.com/definition/grid-computing</ref>. It is also defined as a network of computers used by a single company or organization to solve a problem<ref>http://boinc.berkeley.edu/trac/wiki/DesktopGrid</ref>. Yet another definition as implemented by GridRepublic.org creates a supercomputing grid by using volunteer computers from across the globe<ref>http://www.gridrepublic.org/index.php?page=about</ref>. All of these definitions have something in common, and that is using parallel processing to attack a problem that can be broken up into many pieces.</p><br />
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<p>The following graph generated by data at [www.GridRepublic.Org GridRepublic.org] shows the average processing power of this supercomputer created by volunteers from around the world:</p><br />
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[[File:20120130-grid-computing-graph.png|Image from http://www.gridrepublic.org/index.php?page=stats]]<br />
<p>Image from GridRepublic.org<ref name="grstats">http://www.gridrepublic.org/index.php?page=stats Image from GridRepublic.Org</ref></p><br />
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<p>The GridRepublic.org statistics is for 55 applications running using a total of 10,979,114 GFLOPS or 10,979.114 TFLOPS<ref name="grstats" /></p>.<br />
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= Conclusion/Summary =<br />
<p>Cluster supercomputers account for about twice as much processing in TFLOPS as MPP based supercomputers. The [http://www.GridRepublic.org GridRepublic.org] statistics that it tracks for 55 applications is using about the same amount of processing power as the fastest individual supercomputer listed on the [http://www.TOP500.org TOP500.org] list of supercomputers. The fastest computer listed is the<br />
RIKEN Advanced Institute for Computational Science (AICS) in Japan, which is a K computer, SPARC64 VIIIfx 2.0GHz, Tofu interconnectthat operates at 10510.00 TFLOPS<ref>http://www.top500.org/list/2011/11/100</ref>.</p><br />
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<p>Grid Computing as an alternative to individually defined supercomputers seems to be growing and the expense of operating it is fully distributed across the volunteers that are apart of it. However, with any system where you don't have complete control of its parts, you can't rely on all of those parts being there all the time.</p><br />
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= References =<br />
<p>Your references go here. You should allow the WIKI to create your references list automatically by using inline citations.</p><br />
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<references /></div>Mbplautz