Chapter 6: Joshua Mohundro, Patrick Wong

Sectored Cache

Hard section

Victim Cache

The Victim Cache, in architectures with them, stores just-evicted lines from another level of cache. For speed reasons, this cache is usually direct-mapped and has very few entries, but solves one of the pathological cases for direct-mapped caches, the alternating memory access pattern (of which a cache line conflict occurs). In effect, this extends the associativity of would-be conflict misses by an extra way for very low cost.

Architectures implementing victim cache for x86 include the Transmeta Efficeon, AMD K7, AMD K8, and finally the AMD K10.

AMD has traditionally implemented an exclusive cache hierarchy, a form of cache that avoids duplication of data. Therefore, a victim cache is a natural development from implementation of an exclusive cache.

The K10's "victim cache" deserves some more inspection, as it is at least 2MB big and 32-way set associative; at this point, it is no longer a traditional victim cache and more of a buffer for efficient implementation of AMD's exclusive cache hierarchy. It is possible that AMD decided a traditional, fast victim cache was not beneficial on the K10 architecture and elected to directly use L3 cache as a victim cache.