Chapter 6: Joshua Mohundro, Patrick Wong: Difference between revisions
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The Victim Cache, in architectures with them, stores just-evicted lines from another level of cache. For speed reasons, this cache is usually direct-mapped and has very few entries, but solves one of the pathological cases for direct-mapped caches, the alternating memory access pattern (of which a cache line conflict occurs). In effect, this extends the associativity of would-be conflict misses by an extra way for very low cost. | The Victim Cache, in architectures with them, stores just-evicted lines from another level of cache. For speed reasons, this cache is usually direct-mapped and has very few entries, but solves one of the pathological cases for direct-mapped caches, the alternating memory access pattern (of which a cache line conflict occurs). In effect, this extends the associativity of would-be conflict misses by an extra way for very low cost. | ||
Architectures implementing victim cache for x86 include the AMD K7, K8, and finally K10 | Architectures implementing victim cache for x86 include the Transmeta Efficeon, AMD K7, AMD K8, and finally the AMD K10. | ||
AMD has traditionally implemented an exclusive cache hierarchy, a form of cache that avoids duplication of data. Therefore, a victim cache is a natural development from implementation of an exclusive cache. | |||
The K10's victim cache deserves some more inspection, as it is at least 2MB big and 32-way set associative; at this point, it is no longer a traditional victim cache and more of a buffer for efficient implementation of AMD's exclusive cache hierarchy. | |||
Revision as of 18:44, 30 January 2012
Sectored Cache
Hard section
Victim Cache
The Victim Cache, in architectures with them, stores just-evicted lines from another level of cache. For speed reasons, this cache is usually direct-mapped and has very few entries, but solves one of the pathological cases for direct-mapped caches, the alternating memory access pattern (of which a cache line conflict occurs). In effect, this extends the associativity of would-be conflict misses by an extra way for very low cost.
Architectures implementing victim cache for x86 include the Transmeta Efficeon, AMD K7, AMD K8, and finally the AMD K10.
AMD has traditionally implemented an exclusive cache hierarchy, a form of cache that avoids duplication of data. Therefore, a victim cache is a natural development from implementation of an exclusive cache.
The K10's victim cache deserves some more inspection, as it is at least 2MB big and 32-way set associative; at this point, it is no longer a traditional victim cache and more of a buffer for efficient implementation of AMD's exclusive cache hierarchy.