CSC/ECE 506 Spring 2012/12b sb

On-chip interconnects

Why on-chip interconnects

Driven by continuing scaling of Moore’s law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. On-chip interconnects are attractive due to their regularity and modular design, which can lead to better routability, electrical characteristics and fault tolerance.

References

http://www.cs.utexas.edu/~bgrot/docs/CMP-MSI_08.pdf - Scalable on-chip topologies.

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4341445 - This paper investigates mesh and torus NoC topologies under different routing algorithms and traffic models.

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1639301 - Study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture.

http://www.eecg.toronto.edu/~enright/tilera.pdf - This paper talks about the on-chip interconnection architecture of the Tile Processor.