CSC/ECE 506 Spring 2011/ch6b df
Translation Lookaside Buffer and Cache Addressing
Programs used virtual addresses to access the memory and caches. If the program were to not use virtual addresses, two programs running at the same time would need their own section of the cache. For example, if the computer has a 512MB L1 cache and two programs are running at the same time, each program could only use 256MB of the cache. Virtual addresses are used to allow each program the use of the whole cache. One problem with the programs accessing memory with virtual addresses is that caches and memory need to be accessed with physical addresses. The Operating System is usually used to translate these virtual addresses into physical addresses. The OS can be relatively slow at doing this so we need to create a cache that stores the most recently accessed addresses. This cache is called the Translation Lookaside Buffer or TLB. Virtual addresses are broken up into two parts: a virtual tag and a virtual page offset or VPO. Physical Addresses are broken up into a physical tag and a physical page offset or PPO. The PPO determines which memory page a given value is in. These pages are handled by the OS through page tables. There are three different ways to use the virtual addresses and the physical addresses to access data. THe three ways are physically addressed, virtually addressed, and physically tagged but virtually addressed.
Physically Addressed
Physically Addressed refers to using the whole physical address to access memory. To access memory, the computer must first translate the virtual address into a physical address using the TLB. After the computer has the physical address, it can index through the cache and pull out the block it needs. The computer then checks the tag to see if it is a hit or miss. This is not ideal because the time it takes to access the TLB is added onto the time it takes to access the cache.
Virtually Addressed
Virtually Addressed refers to using the whole virtual address to access memory. The good thing about this is memory and the TLB can be accessed at the same time. The problem with this is that each process has its own virtual page table. So if processor changes from one process to another, the memory still holds the previous process' memory. The new process will not be able to tell the difference between its memory pages and the memory pages of the previous process. In order to solve this problem, the memory and TLB has to be flushed before a new process can be worked on. If processes switch often, the latency required to flush memory may not be ideal.
Physically Tagged but Virtually Addressed
This is where the VPO and the PPO are the exact same and the only thing needing to be translated is the virtual tag into the physical tag. With this model, the TLB and memory can be accessed simultaneously since the PPO is known from the beginning. In this type of addressing, the VPO and virtual tag are split up. The VPO is used to access memory while the virtual tag is sent to the TLB to be translated into the physical tag. This method allows us to access the TLB and memory at the same time without the problem addressed with using the virtual address by itself. There is one problem with this approach. The bits used to specify the set and byte offset are stored within the page offset. Because of this the size of a page has to be greater than the number of sets multiplied by the block size. Given this we find there is a limit on the size of the cache. The maximum cache size is given by the following formula:
MaxCacheSize = PageSize X Associativity
For example you have a cache with the following parameters: page size is 4KB and cache is 2 way set associative with a block size of 32 bytes. A page size of 4KB means 12 bits are needed for the page offset. also, 5 bits are needed for the block offset. This leaves 7 bits to specify the cache set which results in 2^7 or 128 different sets. With the associativity being 2, the maximum cache size is 8KB. This issue is not a big one because caches can not be too big in the first place due to performance constraints.