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18 March 2012
- 14:2814:28, 18 March 2012 diff hist −25 CSC/ECE 506 Spring 2012/8b va →Update and adaptive coherence protocols on real architectures, and power considerations
- 14:1514:15, 18 March 2012 diff hist +35 CSC/ECE 506 Spring 2012/8b va →Simulation result
- 14:1214:12, 18 March 2012 diff hist +24 CSC/ECE 506 Spring 2012/8b va →Simulation result
- 14:0614:06, 18 March 2012 diff hist +487 CSC/ECE 506 Spring 2012/8b va →Simulation result
- 13:5113:51, 18 March 2012 diff hist +378 CSC/ECE 506 Spring 2012/8b va →Update and adaptive coherence protocols on real architectures, and power considerations
- 13:3413:34, 18 March 2012 diff hist +14 CSC/ECE 506 Spring 2012/8b va →Disadvantages of Write-Invalidate Protocol
- 13:2913:29, 18 March 2012 diff hist −3 CSC/ECE 506 Spring 2012/8b va →Example 1
- 13:2713:27, 18 March 2012 diff hist +46 CSC/ECE 506 Spring 2012/8b va →Update and adaptive coherence protocols on real architectures, and power considerations
- 13:2113:21, 18 March 2012 diff hist −12 CSC/ECE 506 Spring 2012/8b va →Update and adaptive coherence protocols on real architectures, and power considerations
- 13:1913:19, 18 March 2012 diff hist +98 CSC/ECE 506 Spring 2012/8b va →Write-Update Protocol
- 13:1813:18, 18 March 2012 diff hist +89 CSC/ECE 506 Spring 2012/8b va →Write-Invalidate Protocol
- 13:1413:14, 18 March 2012 diff hist +25 CSC/ECE 506 Spring 2012/8b va →Coherence protocols:
- 13:0913:09, 18 March 2012 diff hist +1,362 CSC/ECE 506 Spring 2012/8b va →Coherence protocols:
- 13:0413:04, 18 March 2012 diff hist 0 N File:Cache Coherency Generic.png No edit summary
- 12:3812:38, 18 March 2012 diff hist +74 CSC/ECE 506 Spring 2012/8b va →Introduction
- 01:2201:22, 18 March 2012 diff hist +97 CSC/ECE 506 Spring 2012/8b va →Conclusion:
- 01:0601:06, 18 March 2012 diff hist +166 CSC/ECE 506 Spring 2012/8b va →Simulation result:
- 00:5900:59, 18 March 2012 diff hist 0 N File:Image500.png No edit summary current
- 00:5500:55, 18 March 2012 diff hist +30 CSC/ECE 506 Spring 2012/8b va →Subblock states are as follows:
- 00:5400:54, 18 March 2012 diff hist +28 CSC/ECE 506 Spring 2012/8b va →Block states are as follows:
- 00:5200:52, 18 March 2012 diff hist 0 N File:Results summary 3.png No edit summary current
- 00:5200:52, 18 March 2012 diff hist 0 N File:Results summary 2.png No edit summary current
- 00:5100:51, 18 March 2012 diff hist 0 N File:Results summary 1.png No edit summary current
- 00:4800:48, 18 March 2012 diff hist 0 N File:Mp3d.png No edit summary current
- 00:4600:46, 18 March 2012 diff hist 0 N File:Cholesky 128k.png No edit summary current
- 00:4600:46, 18 March 2012 diff hist 0 N File:Gauss 32pro.png No edit summary current
- 00:4500:45, 18 March 2012 diff hist 0 N File:Gauss 128k.png No edit summary current
- 00:4300:43, 18 March 2012 diff hist 0 N File:Subblock protocol.png No edit summary current
- 00:4200:42, 18 March 2012 diff hist 0 N File:Line protocol.png No edit summary current
- 00:0500:05, 18 March 2012 diff hist −134 CSC/ECE 506 Spring 2012/8b va →Simulation result:
- 00:0200:02, 18 March 2012 diff hist 0 N File:Pverify.png No edit summary current
- 00:0200:02, 18 March 2012 diff hist 0 N File:Cholesky.png No edit summary current
- 00:0100:01, 18 March 2012 diff hist 0 N File:Badgauss32.png No edit summary current
- 00:0000:00, 18 March 2012 diff hist 0 N File:Gauss32.png No edit summary current
17 March 2012
- 23:5523:55, 17 March 2012 diff hist +276 CSC/ECE 506 Spring 2012/8b va →Update and adaptive coherence protocols on real architectures, and power considerations
- 22:4522:45, 17 March 2012 diff hist +36 CSC/ECE 506 Spring 2012/8b va →Subblock protocol:
- 22:4222:42, 17 March 2012 diff hist +60 CSC/ECE 506 Spring 2012/8b va →Subblock protocol:
- 22:3722:37, 17 March 2012 diff hist +2 CSC/ECE 506 Spring 2012/8b va →Update and adaptive coherence protocols on real architectures, and power considerations
- 22:2722:27, 17 March 2012 diff hist +4 CSC/ECE 506 Spring 2012/8b va →Update and adaptive coherence protocols on real architectures, and power considerations
- 22:2422:24, 17 March 2012 diff hist +12,036 N CSC/ECE 506 Spring 2012/8b va Created page with "=Update and adaptive coherence protocols on real architectures, and power considerations= ===Introduction=== In a [http://en.wikipedia.org/wiki/Shared_memory shared memory] -..."
7 February 2012
- 04:2504:25, 7 February 2012 diff hist +1,159 CSC/ECE 506 Spring 2012/2a va No edit summary
- 04:1904:19, 7 February 2012 diff hist +3,225 CSC/ECE 506 Spring 2012/2a va No edit summary
- 03:2503:25, 7 February 2012 diff hist −1,255 CSC/ECE 506 Spring 2012/2a va No edit summary
- 03:2303:23, 7 February 2012 diff hist −2,235 CSC/ECE 506 Spring 2012/2a va No edit summary
3 February 2012
- 00:0800:08, 3 February 2012 diff hist −63 CSC/ECE 506 Spring 2012/2a va No edit summary
2 February 2012
- 22:0122:01, 2 February 2012 diff hist +678 CSC/ECE 506 Spring 2012/2a va No edit summary
- 21:4721:47, 2 February 2012 diff hist +110 CSC/ECE 506 Spring 2012/2a va No edit summary
1 February 2012
- 00:5200:52, 1 February 2012 diff hist +4,337 CSC/ECE 506 Spring 2012/2a va No edit summary
22 September 2011
- 02:4702:47, 22 September 2011 diff hist +49 m CSC/ECE 517 Fall 2011/ch2 2f jm →Introduction current
- 02:4402:44, 22 September 2011 diff hist +436 m CSC/ECE 517 Fall 2011/ch2 2f jm →Introduction