CSC/ECE 506 Fall 2007/wiki2 05 sa: Difference between revisions
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! Number of Levels | ! Number of Levels | ||
! Line Size | ! Line Size | ||
! Size | ! Cache Size | ||
! Associativity | ! Associativity | ||
! Coherence Protocol | ! Coherence Protocol | ||
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| Modified Owner Exclusive Shared Invalid (MOESI) | | Modified Owner Exclusive Shared Invalid (MOESI) | ||
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! colspan="6" style="background:#ffdead;" | Singlecore Processors | ! colspan="6" style="background:#ffdead;" | Singlecore Processors | ||
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Revision as of 17:34, 24 September 2007
Cache sizes in multicore architectures
Topic - Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.
| Multicore Processors | |||||
|---|---|---|---|---|---|
| Processor Name | Number of Levels | Line Size | Cache Size | Associativity | Coherence Protocol |
| AMD Athlon 64 FX | 2 | 64 bytes (for both L1 & L2) | L1 - 64KB (Data) + 64KB (Instruction) per core L2 - up to 1 MB per core |
L1 - 2 way (Data and Instruction cache) L2 - 16 way associative |
Modified Owner Exclusive Shared Invalid (MOESI) |
| Singlecore Processors | |||||
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