CSC/ECE 506 Fall 2007/wiki2 05 sa: Difference between revisions

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=<center>Cache sizes in multicore architectures</center>=
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Topic - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.
 
 
{| border="1" cellpadding="5" cellspacing="0" align="center"
|+'''Detail of Caches'''
|-
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
! Processor Name
! Number of Levels
! Line Size
! Cache Size
! Associativity
! Coherence Protocol
|-
| AMD Athlon 64 X2
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 512KB to 1 MB per core
| L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 1 MB per core
| L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
| AMD Athlon Opteron<br/>(marketed for servers)
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 1 MB per core
| L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|- 
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
| colspan="6" style="border-bottom:3px solid grey;" align="center" | Bottom
|-
|}

Latest revision as of 01:51, 25 September 2007

This page was mistakenly created. Please access this page at - http://pg.ece.ncsu.edu/mediawiki/index.php/CSC/ECE_506_Fall_2007/wiki2_5_as