CSC/ECE 506 Fall 2007/wiki2 05 sa: Difference between revisions

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=<center>Cache sizes in multicore architectures</center>=
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Topic - Create a table of caches used in current multicore architectures,
including such parameters as number of levels, line size, size and
associativity of each level, latency of each level, whether each level
is shared, and coherence protocol used. Compare this with two or three
recent single-core designs.

Latest revision as of 01:51, 25 September 2007

This page was mistakenly created. Please access this page at - http://pg.ece.ncsu.edu/mediawiki/index.php/CSC/ECE_506_Fall_2007/wiki2_5_as